GOF DEBUG / INTERACTIVE NETLIST SCHEMATIC

Large netlist.
Clear schematic. Fast answers.

See the logic behind your signals. GOF Debug lets IC designers build schematics dynamically, make GUI ECOs on the fly, and trace deep clock buffer paths—in the same visual workspace.

Request a GOF Debug license Watch the schematic demos

01 / DYNAMIC SCHEMATIC

The report names an instance.
See the logic around it.

In a large netlist, a debug investigation often starts with one instance:

DFT DRC: trace the flagged instance in the schematic to understand the violation. Once the required fix is clear, make the ECO right there—see ECO on the fly in Figure 2.
Timing analysis: excessive delay through a cell contributes to a timing violation.
Gate-level timing simulation: a timing check reports a violation at a flip-flop instance.

That instance may be buried many levels deep in the design hierarchy. Tracing its connections through module definitions and port mappings in a text editor is slow and difficult.

With GOF Debug, copy the full instance name from the report and use Ctrl + g to open it in a schematic. Expand its drivers and loads with mouse clicks to inspect the surrounding logic and understand the reported issue.

Watch Figure 1: a single flip-flop grows into a connected schematic as the user expands its input and output paths.

Explore the schematic tools in the manual →

Schematic of a flip-flop with its input drivers and output loads expanded in GOF Debug. — **Figure 1.** Build a schematic dynamically from the part of the netlist you are investigating. View full-size animation ↗

From report to schematic in three steps

Load your design once, then jump straight to a reported instance—even when its hierarchy path is long.

Start GOF with your design.Load the cell libraries and netlist:
```
gof -lib t65nm.lib -lib io.lib netlist_port.v
```
Replace these example filenames with your own.
Copy the full instance name.Copy its complete hierarchical path from the DFT, timing, or simulation report to the clipboard.
Press Ctrl+g, then click OK.In the GofViewer netlist window, press Ctrl + g. The dialog is prefilled with the copied instance name. Click OK to load it into the schematic and start tracing.

GOF manual §2.9.1: Start up GOF in GUI Mode →

02 / GUI ECO

Find the cause.
Fix it in the same schematic.

After tracing an instance flagged by DFT DRC, you can move straight from understanding the issue to making the required logic change. Enable ECO mode in the same schematic, insert a gate or reconnect pins, and inspect the updated connections on the fly.

Debug and ECO in one schematic. This is a key advantage of GOF Debug: the circuit context you used to diagnose the problem becomes the workspace for the fix.

Watch Figure 2: the user inserts a NAND gate into an existing path and connects another signal to its input, building the ECO on the fly.

Explore GUI ECO in the manual →

GUI ECO schematic showing a newly inserted NAND gate and its input and output connections. — **Figure 2.** Insert and connect a gate directly in the schematic for a focused GUI ECO. View full-size animation ↗

03 / CLOCK TREE DEBUG

Trace deep clock trees.
Skip the repetitive clicks.

Finding the source of a clock in a huge buffer tree can mean following stage after stage. GOF Debug automates that upstream trace.

Select a flip-flop’s clock input and choose Driver Until Non Buffer. GOF follows the buffer and inverter chain until it reaches a non-buffer/inverter driver, drawing the path for inspection.

Watch Figure 3: one command expands the clock input’s upstream buffer path. The trace follows the selected path through the tree.

Read the clock tracing workflow in the manual →