Netlist Debug/Report

• Find equal nets in Implementation Netlist For Reference RTL wire
• Net names collision in Verilog to Spice conversion
• Clock tree fast trace
• Debug non-equivalent points after ECO
• Design Statistic
• Graphic mode vs Text mode
• Calculate clock gating percentage
• Debug Connectivity (PDF)
• Flexible Schematic generator
• Script Mode Modify State Machine and Debug
• Layout Placement Regions View
• Circuit Placement View on Layout