Debug Non-equivalent Points After ECO
The use case shows how to debug non-equivalent points after automatic functional ECO. Check the previous automatic function ECO example.
Add Schematic Command into ECO Script
# GofCall ECO script, auto_eco.pl use strict; undo_eco; # Discard previous ECO operations setup_eco("eco_example"); # Setup ECO name read_library("art.90nm.lib"); # Read in standard library # Read in the Reference Netlist which is re-synthesized with several modules modified read_design("-ref", "reference.gv"); # Read in the netlist file after ECO read_design("-imp", "eco_verilog.v"); set_top("topmod"); # Set the top module set_ignore_output("TEST_SO*"); # To avoid test lockup to affect the ECO result set_pin_constant("TEST_EN",0); # To avoid test logic being touched sch("moda/submoda/usaa/usaax/sa_reg1", "-both"); # Load the failing point from both netlists exit;
Debug On Schematic
The 'sch' command with '-both' option loads the instance under debug from both netlists to the schematic.
Figure 1: Flops from both netlists
It's helpful to check if the flatten fanin points are matching between two netlists. To do that, select 'D' pin and right click to select 'List Flatten Fanin Endpoints'.
Figure 2: Do flatten Fanin Endpoints analysis
A pop window shows the flatten fanin endpoints for IMP netlist.
Figure 3: IMP Endpoints
Do the same for REF instance.
Figure 4: REF Endpoints
In most cases, they should match for equivalent points. If they don't match and the flop instance is not equivalent, it can tell the cause in fast way.
Press 'ctrl' key and click 'D' pins of both instances. Right click to select "Equivalence Check for 'ai' vs 'ai'".
Figure 5: Equivalence Check Command
A pop window shows the equivalence check result. It's not equivalent.
Figure 6: Not Equivalent Result
Continue to expand the schematic. A fast schematic expanding way is to use 'Show until non-buffer on Schematic' which can loads all cells in the driver path until it meets a non-buffer cell.
Figure 7: Use Fast Schematic Way
The fast Schematic expanding way loads all buffers, inverts and connectors until it meets non-buffer (XOR)
Figure 8: Fast Schematic Expanding Result
Expand the schematic by using the fast way or by clicking mouse middle-button on input pins. And keep on check the equivalence of related pins.
Figure 9: Expanding Schematic
When checking the equivalence of 'zzsx' to 'zzsx', it shows they are different and the root cause is one driver is XOR gate the other is OR gate.
Figure 10: Find Root Cause