A Practical Way to Do Netlist ECO & Debug

Gated-clock is one very important methodology used in low power design. But gated-clocks incur more clock skew, the backend tools will add a lot of clock cells in clock trees in order to balance skew between two gated-clocks and fix hold timing violations. In low power logic design, it should avoid too many clock cells being inserted in clock trees.  The solution is to add reverse edge Flip-Flops between two gated-clocks. It's not good idea to add all of the reverse edge Flip-Flops in RTL. It would be better to add some of them in timing closure ECO. Only when hold timing violation happens.

  • Look at the following schematic.
  • The first gated-clock generates ndNet_2_0 and going through pipeline to the Flip-Flops clocked by the second gated-clock net110395_clk.
  • There is hold timing violation in the pipeline stage. ECO is needed.

  • Enable ECO mode.
  • Select five lines connect to D inputs of the target Flip-Flops.


  • Enter cell number to insert in one line.


  • Select p_SDFFNPRHX4, click OK.


  • Select proper connectivities.


  • The final ECOed schematic is shown below.

  • The ECO result in Synopsys TCL format is listed.


current_design TM_P_sf
disconnect_net [get_nets N470] [get_pins curindex_reg_4_/D]
disconnect_net [get_nets N466] [get_pins curindex_reg_0_/D]
disconnect_net [get_nets N468] [get_pins curindex_reg_2_/D]
disconnect_net [get_nets N469] [get_pins curindex_reg_3_/D]
disconnect_net [get_nets N467] [get_pins curindex_reg_1_/D]
create_cell eco012345_ECOCELL_4 artisan_tsmc90lp_hv.synth/p_SDFFNPRHX4
create_cell eco012345_ECOCELL_1 artisan_tsmc90lp_hv.synth/p_SDFFNPRHX4
create_cell eco012345_ECOCELL_0 artisan_tsmc90lp_hv.synth/p_SDFFNPRHX4
create_cell eco012345_ECOCELL_3 artisan_tsmc90lp_hv.synth/p_SDFFNPRHX4
create_cell eco012345_ECOCELL_2 artisan_tsmc90lp_hv.synth/p_SDFFNPRHX4
create_net N466_eco012345_19
create_net N469_eco012345_16
create_net N468_eco012345_15
create_net N467_eco012345_18
create_net N470_eco012345_17
connect_net [get_nets ndNET_1_ECK] [get_pins eco012345_ECOCELL_1/CKN]
connect_net [get_nets N469_eco012345_16] [get_pins eco012345_ECOCELL_1/Q]
connect_net [get_nets N469] [get_pins eco012345_ECOCELL_1/D]
connect_net [get_nets ndNET_1_ECK] [get_pins eco012345_ECOCELL_0/CKN]
connect_net [get_nets N468_eco012345_15] [get_pins eco012345_ECOCELL_0/Q]
connect_net [get_nets N468] [get_pins eco012345_ECOCELL_0/D]
connect_net [get_nets ndNET_1_ECK] [get_pins eco012345_ECOCELL_2/CKN]
connect_net [get_nets N470_eco012345_17] [get_pins eco012345_ECOCELL_2/Q]
connect_net [get_nets N470] [get_pins eco012345_ECOCELL_2/D]
connect_net [get_nets ndNET_1_ECK] [get_pins eco012345_ECOCELL_4/CKN]
connect_net [get_nets N466_eco012345_19] [get_pins eco012345_ECOCELL_4/Q]
connect_net [get_nets N466] [get_pins eco012345_ECOCELL_4/D]
connect_net [get_nets ndNET_1_ECK] [get_pins eco012345_ECOCELL_3/CKN]
connect_net [get_nets N467_eco012345_18] [get_pins eco012345_ECOCELL_3/Q]
connect_net [get_nets N467] [get_pins eco012345_ECOCELL_3/D]
connect_net [get_nets N470_eco012345_17] [get_pins curindex_reg_4_/D]
connect_net [get_nets N468_eco012345_15] [get_pins curindex_reg_2_/D]
connect_net [get_nets N469_eco012345_16] [get_pins curindex_reg_3_/D]
connect_net [get_nets N467_eco012345_18] [get_pins curindex_reg_1_/D]
connect_net [get_nets N466_eco012345_19] [get_pins curindex_reg_0_/D]
connect_net [get_nets gbrstn] [get_pins curindex_reg_4_/RN]
connect_net [get_nets gbrstn] [get_pins curindex_reg_2_/RN]
connect_net [get_nets gbrstn] [get_pins curindex_reg_3_/RN]
connect_net [get_nets gbrstn] [get_pins curindex_reg_1_/RN]
connect_net [get_nets gbrstn] [get_pins curindex_reg_0_/RN]


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