Metal Configurable Gate Array ECO

Metal configurable gate array cells are specially developed for Metal Only ECO. There are two types of gate array cells used in different backend stages. The first type is gate array spare cells which are normal filler or decap cells in the original flow. In the backend P&R stage, gate array spare cells, like GFILL/GDCAP, are added and scattered over the design. The second type is gate array functional cells. In post-mask ECO, gate array spare cells are swapped out by gate array functional cells, like GAN2, GND2, GXOR2.

Gate Array Cell Base Tile

The base unit of gate array cell is a tile. Every gate array cell consists of one or more tiles. Use one 5nm standard library as example:

Tile NumbersSpare CellsFunctional Cells

Table: Tile Numbers in Gate Array Spare Cells and Functional Cells

Gate array cells are larger than the normal standard cells. For example, GFILL1 is four times larger than FILL1 and GND2D1 is 25% larger than ND2D1. The power consumption and timing are similar.

Each gate array spare cell has the location defined by DEF file. As shown in Figure 1, one GFILL8 spare cell has location defined as (Xg, Yg). The tile width is the width of GFILL1.

The tiles on the GFILL8 can be regrouped and rewired in metal layers to form different functional cells. For example, GBUFD1 takes two tiles and implements buffer function and GAN4D1 takes 3 tiles to form 4 inputs AND function.

Figure 1: Gate Array Spare Cell GFILL8 Regrouped Tiles to Form Functional Cells

Automatic Mapping

When GOF generates a patch, it synthesizes the patch to gate array functional cell types only. Then the gate array functional cells are mapped to the optimal close by gate array spare cells with minimum wire connection costs.

Figure 2: Gate Array Spare Cells Mapping to Functional Cells

After mapping and swapping, as shown in Figure 2, some gate array spare cells have portion of tiles being used by several functional cells. When saving ECO results, these gate array spare cells should have type changed, for instance, gate array A should have type changed from GFILL8 to GFILL4. Those used up gate array spare cells should be deleted, for instance gate array B has type GFILL4 and all four tiles are used.

The mapped gate array functional cells should be moved to the locations of the corresponding gate array spare cells, and horizontal location X should be adjusted according to the starting tile location. As shown in Figure 1, GINVD1 instance should be moved to (Xg+TW, Yg) and GBUFFD1 instance should be moved to (Xg+TW*6, Yg).

GOF writes out ECO verilog file and Backend tools ECO scripts. In Verilog file, the newly added gate array functional cells have location written in comments. GOF supports Synopsys ICC script and Cadence Encounter script. Both scripts have cell location placement support.

For example, saving the result in ICC TCL script, the cells in Figure 1 have the following commands:

size_cell GFILLER_7256 GFILL1 # The original GFILL8 resized
create_cell eco_3821_ubuf GBUFD1
create_cell eco_3821_uan4 GAN4D1
create_cell eco_3821_und2 GND2D1
create_cell eco_3821_uinv GINVD1
set_cell_location -ignore_fixed -coordinates "255.02 413.28" eco_3821_ubuf # Xg+WT*6, Yg
set_cell_location -ignore_fixed -coordinates "254.42 413.28" eco_3821_uan4 # Xg+WT*3, Yg
set_cell_location -ignore_fixed -coordinates "254.22 413.28" eco_3821_und2 # Xg+WT*2, Yg
set_cell_location -ignore_fixed -coordinates "254.02 413.28" eco_3821_uinv # Xg+WT*1, Yg

Encounter script format:

ecoChangeCell -inst GFILLER_7256 -cell GFILL1 # The original GFILL8 resized
addInst -loc 255.02 413.28 -inst eco_3821_ubuf -cell GBUFD1 # Xg+WT*6, Yg
addInst -loc 254.42 413.28 -inst eco_3821_uan4 -cell GAN4D1 # Xg+WT*3, Yg
addInst -loc 254.22 413.28 -inst eco_3821_und2 -cell GND2D1 # Xg+WT*2, Yg
addInst -loc 254.02 413.28 -inst eco_3821_uinv -cell GINVD1 # Xg+WT*1, Yg

Note:Tile size assumed to be 0.20 X 0.22; GFILL8 location (Xg, Yg)=(253.82, 413.28)

Gate Array Spare Cells ECO vs Standard Spare Cells Case

The experimental design has both gate array spare cells and standard spare cells inserted. In the placement shown in Figure 3, the gate array spare cells are highlighted in green and the standard spare cells are highlighted in red. It shows, there are much more gate array spare cells distribution than standard spare cells. Also one gate array cell can be used as any functional cell as long as it has the same or more number of tiles than the gate array functional cell. So gate array spare cells ECO is much more easier to accomplish than standard spare cells.

Figure 3: Gate Array Spare Cells vs Standard Spare Cells Distribution

The gate array spare cells ECO has ~70 gate array functional cells added. The wire connections are well concentrating in one location as shown in Figure 4.

Figure 4: Gate Array ECO Gates Connections Concentrating in One Area

The standard spare cells ECO has ~90 spare gates used. The utilized spare gates scatter over a large area. Figure 5 has comparison of the two ECO placement and wiring. The gate array ECO has very concentrated ECO area as indicated by red color. But the standard spare cells ECO spreads over a large area as shown in blue in Figure.

Figure 5: Placement and Wiring Comparison of Gate Array Cells ECO and Standard Spare Cells ECO

Check Metal Configurable Gate Array Cells ECO for detail

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