Conformal ECO performs poorly in boundary optimized netlist from Design Compiler Topographical mode synthesis. It adds more than necessary gates in the DCT/DCG netlist ECO.
Synopsys Design Compiler Topographical(DCT) or Design Compiler Graphical(DCG) optimizes netlist for floorplanning, routing and timing, but it brings difficulties in functional ECO. During synthesis, the hierarchical module boundaries are changed to add clone ports or invert the original ports phase and flops may be merged.
Conformal ECO makes wrong ports mapping in functional ECO. As shown in Figure 1, Conformal ECO makes wrong mapping in the clone ports added by DCG/DCT and it produces 3X more gate counts than necessity in fixing the logic.
Figure 1: Boundary mapping affects ECO quality
The synthesis tool adds cloned ports, but they are not one to one mapping between the Reference Netlist and the Implementation Netlist. When the ECO tool forces to make these ports equal, it brings redundant gates to the ECO patch or it even makes the final logic not equivalent.
Figure 2: DCG/DCT Boundary optimized netlist
GOF maps the clone ports properly and only the exact non-equivalent point is fixed.
Figure 3: GOF result, only the red spot is fixed
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