Full layers functional ECO can add or delete gates freely. The ECO operations are done in ECO script which is compatible with Perl, and it uses exported APIs to access, modify and save the netlist database. GOF reads in two netlist files, Implementation Netlist which is under ECO and Reference Netlist which is re-synthesized from modified RTL with the same constraints as the pre-layout netlist. In the ECO script, the API 'fix_design' is used to fix the top level module and its sub-modules in global mode. GOF uses the built-in Logic Equivalent Check Engine to figure out the non-equivalent points. And optimized minimum size gate patches are applied to fix the non-equivalent modules.
As shown in Figure 1, two logic cones are extracted from the Implementation and Reference Netlist for the same compare point. The implementation point mismatches the reference point initially. GOF compares the two points and generated a patch from Reference logic cone and applies to Implementation Netlist. After the patching, the two points become equivalent.
Figure 1: Logic Cone Optimization
GOF does logic cone analysis and optimization for each failing point found in top down logic equivalence check. The failing point is in the format of output port or sequential element's input pin, such as flop's D input. The final patch has the minimum number of gates to make the implementation logic cone equal to the reference logic cone.
The flow chart is shown in Figure 2.
Figure 2: Automatic functional ECO flow
Steps for an automatic functional ECO:
The ECO script has exact the same syntax of Perl script. It runs the exported APIs that access the netlist database and modify the netlist.
The following is the example script for automatic functional ECO:
# GofCall ECO script, run_example.pl use strict; undo_eco; # Discard previous ECO operations setup_eco("eco_example");# Setup ECO name read_library("art.5nm.lib");# Read in standard library read_svf("-ref", "reference.svf.txt"); # Optional, must be loaded before read_design, must be in text format\n"; read_svf("-imp", "implementation.svf.txt"); # Optional, must be loaded before read_design, must be in text format\n"; read_design("-ref", "reference.gv");# Read in Reference Netlist read_design("-imp", "implementation.gv");# Read in Implementation Netlist Which is under ECO set_top("topmod");# Set the top module # Preserve DFT Test Logic set_ignore_output("scan_out*"); set_pin_constant("scan_enable", 0); set_pin_constant("scan_mode", 0); fix_design; save_session("current_eco_name"); # Save a session for future restoration report_eco(); # ECO report check_design("-eco");# Check if the ECO causes any issue, like floating write_verilog("eco_verilog.v");# Write out ECO result in Verilog exit; # Exit when the ECO is done, comment it out to go to interactive mode when 'GOF >' appears
SVF files can help key point mapping when the design involves multibit flops or massive name changes. Multibit flops are used to decrease silicon area and reduce power consumption. But each synthesis process can have different single bit flop instance combinations in each multibit flop instance and combining with the name changes, it causes difficulties in key point mapping. Also backend tools may split or merge multibit flops. So it is highly recommended to load SVF files if the design involves multibit flops. See the section 'Multibit flops in ECO' for more detail.
The ECO Script can be run by '-run' option.
Check Run and debug ECO script section in User Manual for more detail
The example is in the released package.
To run the example:
The log file shows there are total 35 gates in the initial logic cone. After optimization, the patch has only 1 complex cell and 8 inverts
