1. What is power gating?

2. What should be done to power gated partitions?

3. How to verify power implementation?

1. What is power gating?

Power gating is to shut off the power of a cluster of gates on the die to save leakage current. With respect to total power consumption, leakage power has increased to to over 50 percent in 65-nm designs, power gating methodology is adopted by more and more design companies. The basic method is shutting the external power but it's slow. The more comprehensive way is to make power controllable inside the chip which is much fast to power on off. Practically the power is controlled by PMOS/NMOS transistors. And NMOS is picked against PMOS since it has fast response time and driver capability than PMOS. And the selection of NMOS makes GND controllable not VDD.

2. What should be done to the power gated partitions?

P&R side has to implement the NMOS control mechanism and other power rails layout. This topic is focus on netlist side.

The power gated partition should have isolation logic for the output ports to other non power gated partitions. The isolation logic is basically an AND gate. Every output port from power gated partition to non power gated partition should have an AND gate to isolate the "floating" wire. The "floating" wire is charging slowly to the value of VDD when the partition is gated off. And the "floating" wire has high driver impedance.

The power gated partition should have some Always On Logic which can't be shut off by the NMOS, that is to say, their GND is not controlled by NMOS, but real power ground instead. The feeding through paths and the NMOS control signal have to use Always On Logic in order to retain the right value in power gated mode. If the isolating AND gate is in power gate partition, it has to be always on too. These Always On Logic requires a new set of library with different naming for easy detection in verification stage.

Power nets, GND VDD or other gated GND, should be explicitly present in the netlist in order to verify the power implementation.

3. How to verify the power implementation?

The isolation AND gates and the always on logic should be checked as implemented correctly. If the isolation AND gates are inserted after synthesis, the enable input of the AND gate is set to disabled value in Logic Equivalence Check. So these AND gates are not covered in formal run in this case. But even the isolation AND gates already exist in RTL, there is still a need to check they are correctly implemented in the netlists.

The common issues for power gating flow in timing closure stage includes:

• Always On Logics are corrupted by various EDA tools that have processed the netlists.
• Isolation AND gates are missing for new added logic.

Case 1 can't be fixed by the EDA tools themselves, since you can't ask all EDA tools to recognize the Always On Logic paths. So the post-processing script becomes a practical choice.

GofCall scripts can be used in verifying and fixing the issues.

For the feeding through paths to be always on:

1. set_top("power_gated_module1");
2. my @outports = get_ports("-output", "*");
3. OPORT: foreach $port (@outports){
4.     my @driver = get_driver($port);
5.     my $inst = $driver[0];
6.     my $pin_name = $driver[1];
7.     my $type = $driver[2];
8.     my $leaf_ref = get_ref($inst);
9.     my @feed_through_cells  = ();
10.     while(1){
11.         if($type eq "port"){  # reach the input port, found to be feeding through
12.              last;
13.         }
14.         my @gate_type = get_leaf_type($leaf_ref); # check if it is buffer
15.         if(@gate_type == 1 && $gate_type[0] eq "buf"){
16.              push @feed_through_cells, [$inst, $leaf_ref];
17.              my @pins = get_pins("input", $inst);
18.              my @new_driver = get_driver($pins[0]); # buffer's input pin has only one
19.              $inst = $new_driver[0];
20.              $type = $new_driver[2];
21.              $leaf_ref = get_ref($inst);
22.          }else{
23.              next OPORT;
24.          }
25.       } # end of
26.       # The feeding through path is found and saved in feed_through_cells array
27.       foreach my $item (@feed_through_cells){
28.          my $f_inst = $item->[0];
29.          my $f_ref = $item->[1];
30.          my $always_on = get_cell_info("-attribute","always_on",$f_ref);
31.          if(!$always_on){
32.             print "ERROR! $f_inst $f_ref is corrupt in $port feed through path\n";
33.             my $the_right = "PO_$f_ref";
34.             change_gate($f_inst, $the_right, "");  # fix it right away
35.           }
36.       }
37.  }