Gates On the Fly implements several cutting edge ECO methodologies. Netlist ECO varies in size and complexity from case to case. Design process changes from company to company. Gates On the Fly gives users flexibility to choose one or several of the methodologies depending on the size and complexity of the changes.

ü Automatic ECO and Manual ECO.

ü Script Mode and GUI Mode.

ü Metal Only ECO and All Layers ECO.

ü Functional ECO and Timing ECO.

Automatic mode ECO

The automatic ECO is done by a GofCall script. The flow needs the implementation netlist which is under ECO, and the reference netlist which is re-synthesized from modified RTL. Users provide the non-equivalent points reported by LEC to the tool. GOF uses the built-in Logic Equivalence Check engine to analyze the logic cones of the non-equivalent points and fully utilize any existing logic resource to fix the logic cone in the implementation netlist. The final patch is optimized circuit with minimum gate count that make the logic cone in the implementation netlist equal to the logic cone in the reference netlist. The patch gates can be all spare gates if the '-metalonly' option is enabled. Timing ECO can be done in automatic mode as well. Primetime report file is needed in automatic timing ECO.

Manual mode ECO

When ECO changes are known and ECO size is small or the operations are repetitive like adding inverts on a bus, manual mode ECO is better choice. Since it is more efficient and the final gates touched can be less than automatic mode ECO. Moreover, automatic and manual mode ECO can be interleaved in one GofCall ECO script.

Metal Only ECO

Users can specify the spare gates type in GofCall script and enable ‘-metalonly’ option to tell GOF only use the spare gates for the newly added cells. The flow can be in automatic or manual mode.

Hierarchical ECO

GOF supports hierarchical ECO by set the ECO scope the sub-modules. Some Logic Equivalence Check cases can only be resolved in flatten mode. Since GOF only focuses on the spots that user specifies, it can avoid to fall into the trap of LEC failing in hierarchical netlist.

Timing ECO

GOF reads in Primetime report file and does bottleneck analysis of the violations. The critical path is automatically fixed. User can choose to do timing ECO manually with ECO APIs.

GUI mode ECO

GUI mode ECO has advantage of fast ramping up. It’s good for small size ECO. The incremental schematic feature is very helpful for analyzing the netlist before the next step is decided.

Integrated environment

The incremental schematic is very useful in pinpointing the logic issues. GOF has exports many useful APIs to fast access the database.

In section 2, eight ECO flows are listed to accommodate different ECO scenarios. In section 3, a guideline is provided for choosing the ECO flow.

2 Netlist ECO Flows

2.1 Automatic All Layers Functional ECO Flow

2.1.1 Overview

The ECO operations are done in a GofCall script which is compatible with Perl, and it uses exported APIs to access the netlist database. GOF reads the implementation netlist which is under ECO and the reference netlist which is re-synthesized from modified RTL. In the GofCall script, the failing points reported by Logic Equivalent Check Tool are specified. GOF uses the built-in Logic Equivalent Check Engine to figure out the minimum number of patch gates to fix the failing point.

Figure1 shows two logic cones from the implementation and reference netlist for the same compare point. The implementation point mismatches the reference point initially. GOF compares the two points and extracts the patch logic from the reference netlist and applies to the implementation netlist. After the patching, the two points become equivalent.

Figure 1 Logic Cone Optimization

GOF does logic cone analysis and optimization for each failing point user specifies. The failing point is in format of output port or sequential element’s input pin, such as flop’s D input. The final patch is the minimum number of gates to make the implementation logic cone equal to the reference logic cone.

The flow chart is shown in Figure 2.

Figure 2, Automatic functional ECO flow

2.1.2 Files and data requirements

Standard library (Synopsys Liberty) files with extension '.lib'.
Other Verilog libraries files.
Implementation Netlist on which ECO will be done.
Reference Netlist.
The non-equivalent points reported by LEC tool. They are either output ports or sequential cells’ input pin. E.G. 'dout', 'state_reg/D'.
Note: In non-equivalent points list, if pin name is not specified in instance case, input data pins are assumed. E.G. 'fix_logic("state_reg")' and state_reg has data pin 'D' and 'E', the command is the same as 'fix_logic("state_reg/D", "state_reg/E")'.

2.1.3 Steps to do automatic functional ECO

A typical situation for an automatic functional ECO:

Synthesize the new RTL to get Reference Netlist
Run LEC on Reference Netlist to Implementation Netlist.
Collect the failing points in the above run.
Draft a GofCall:

§ Specify ECO name in 'setup_eco'.

§ Load Standard Cell libraries and Verilog libraries.

§ Load Reference Netlist and Implementation Netlist.

§ Specify the failing points in 'fix_logic' command.

§ Add other manual ECO commands before or after 'fix_logic' if needed.

Run the script to execute ‘fix_logic’ command.
Report ECO status and write out ECO results.

2.1.4 Example GofCall scripts

The GofCall script has exact the same syntax of Perl script. But it can execute exported APIs that access the netlist database and modify the netlist.

The following shows an example of an automatic functional ECO:

# GofCall ECO script, run_example.pl

use strict;

undo_eco; # Discard previous ECO operations

setup_eco("eco_example"); # Setup ECO name

read_library("art.90nm.lib"); # Read in standard library

read_design("-ref", "reference.gv"); # Read in the Reference Netlist

read_design("-imp", "implementation.gv"); # Read in the implementation Netlist Which is under ECO

set_top("topmod"); # Set the top module that ECO is working on

# die; # User can uncomment out ‘die’ to let GOF stop here and do interactive debugs

my @fixpoints; # Define the fix points

push @fixpoints, "state_reg_0_/D"; # Fill in the failing point reported from LEC tool

# '/D' can be omitted, the tool would assume all data input pins

push @fixpoints, "state_reg_1_/D"; # Fill in the failing point reported from LEC tool

fix_logic(@fixpoints); # Execute fix_logic command to fix all the failing points

report_eco(); # ECO report

write_verilog("eco_verilog.v"); # Write out ECO result in Verilog

write_soce("eco_soce.tcl"); # Write out TCL script for SOC Encounter

exit; # Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.1.5 Run and debug

The GofCall Script can be run by ‘-run’ option.

gof -run run_example.pl

Check Run and debug GofCall script section for more detail

2.1.6 New ports and registers

2.1.6.1 New output ports

Any new output ports and registers should be added in 'fix_logic' argument list. For example, if new output port, 'out_port0' and 'out_port1' are new in Reference Netlist and not present in Implementation Netlist.

fix_logic('out_port0', 'out_port1');

2.1.6.2 New registers

Same as new output ports, any new registers should be added in 'fix_logic' argument list. For example, if output port 'out_port' and register 'state_reg_new' are new in Reference Netlist and not present in Implementation Netlist. Specify new register's input pins in the command.

fix_logic('out_port', 'state_reg_new/D', 'stat_reg_new/CK');

However, clock pin and reset/set/test_enable pins of the new flop normally don't connect to clock tree or reset tree in Reference Netlist, since Reference Netlist has gone through re-synthesis process. So the alternative is to do manual connections after 'fix_logic'. Connect clock and reset/set/test_enable pins to other existing register.

fix_logic('out_port', 'state_reg_new/D');

change_pin('state_reg_new/CK', 'state_reg_7_/CK');

change_pin('state_reg_new/RN', 'state_reg_7_/RN');

change_pin('state_reg_new/SE', 'state_reg_7_/SE');

2.1.6.3 Stitch new flops into scan chain

Scan chain can be updated to insert the new flops. 'stitch_scan_chain' command can be used to automatically stitch up the new flops.

fix_logic('out_port', 'state_reg_new/D');

change_pin('state_reg_new/CK', 'state_reg_7_/CK');

change_pin('state_reg_new/RN', 'state_reg_7_/RN');

change_pin('state_reg_new/SE', 'state_reg_7_/SE');

# The new flop 'state_reg_new' will be inserted into scan chain before 'state_reg_7_'

# The scan chain can be reconnect up by manual change_pin commands as well

stitch_scan_chain('state_reg_7_');

2.1.6.4 New input ports

There is no need to do anything for new input ports in the current module. However, the logic in parent module has to be fixed. The 'Multiply modules in hierarchical netlist' section describes this case.

2.1.7 Dedicated Logic Equivalence Check Engine

The built-in Logic Equivalence Check Engine is dedicated to search equivalent nets in the implementation netlist to optimize the patch circuit. The searching process is global.

Figure 3 Dedicated LEC Engine

For each net in the Reference Logic Cone, any net in the Implementation Logic Cone with the same fanin end-points will be compared for Logic Equivalence.

An API 'comare_nets' can be used to compare any two nets in the reference netlist and the implementation netlist.

Compare_nets API:

Check equivalence of two nets in the reference and implementation netlist

Usage: my $result = compare_net($net0, $net1);

$net0: The net in the reference netlist.

$net1: The net in the implementation netlist.

$result: If 1, they are equal, if 0, they are not equal.

Examples:

# Compare reg1/D in the reference and reg1/D in the implementation netlist

compare_nets("reg1/D", "reg1/D");

Since the Logic Equivalence Check engine compares every net in the logic cone, it makes very easy to debug logic equivalence mismatches in two netlists. Read two nets equivalence check in GUI mode for more detail.

2.1.8 Multiple modules in hierarchical netlist

In hierarchical netlist, each module having failing point should be set the scope by 'set_top' command and do 'fix_logic' respectively.

For example, module 'top' has sub-module 'smod'. 'smod' has flop 'state_reg_0_' changed and new input port 'in0' added.

Port 'in0' is automatically added by 'fix_logic' command in module 'smod'. However in the parent module 'top', the 'smod' instance's input pin 'in0' should be fixed. Line 12 and line 13 in the following script are to fix the parent module 'top'.

Figure 4 Across multiple modules

1. # GofCall ECO script, run_hier_example.pl

2. use strict;

3. undo_eco; # Discard previous ECO operations

4. setup_eco("eco_hier_example"); # Setup ECO name

5. read_library("art.90nm.lib"); # Read in standard library

6. read_design("-ref", "reference.gv"); # Read in the Reference Netlist

7. # Read in the implementation netlist which is under ECO

8. read_design("-imp", "implementation.gv");

9. set_top('smod'); # First set the scope to 'smod'

10. # Fix the logic of state_reg_0_ in 'smod', note 'in0' is automatically added

11. fix_logic('state_reg_0_/D');

12. set_top('top'); # Set the scope to parent of 'smod'

13. fix_logic('u_smod/in0', 'top_state_reg_0/D'); # Do logic fix in this scope

14. report_eco(); # ECO report

15. write_verilog("eco_verilog.v"); # Write out ECO result in Verilog

16. write_soce("eco_soce.tcl"); # Write out TCL script for SOC Encounter

2.1.9 Module Bound ary optimized handling

Hierarchical netlist may have module boundary optimized after Backend Place and Route. GOF can detect the optimizations when comparing the implementation netlist to the reference netlist . The built-in Logic Equivalence Check Engine takes the optimized logics into consideration when creating patch circuit.

2.1.9.1 Optimization example

One of the common module boundary cases is invert moved across the module boundary. For example,

Pre-layout netlist has these codes

1. module top(a,b,c);

2. input a,b;

3. output c;

4. wire b_inv;

5. INVX2 U0(.A(b),.Y(b_inv));

6. smod smod(.a(a),.b(b_inv),.c(c));

7. endmodule

8. // sub-module

9. module smod(a,b,c);

10. input a,b;

11. output c;

12. ANDX2 U0(.A(a), .B(b), .Y(c));

13. Endmodule

Post-layout netlist has module boundary optimized for sub-module 'smod' port 'b'. The invert is moved into sub-module 'smod'

1. module top(a,b,c);

2. input a,b;

3. output c;

4. smod smod(.a(a),.b(b),.c(c));

5. endmodule

6. // Sub-module

7. module smod(a,b,c);

8. input a,b;

9. output c;

10. wire b_inv_FE;

11. INVX2 U1(.A(b), .Y(b_inv_FE));

12. ANDX2 U0(.A(a), .B(b_FE), .Y(c));

13. endmodule

2.1.9.2 Module level Logic Equivalence Check

The post-layout netlist matches the pre-layout netlist when check the Logic Equivalence from 'top' in flatten mode. However, when set the scope to 'smod', the module is NOT equivalent if the optimization is not taken into consideration.

GOF always checks boundary optimization when the current module scope is set to sub-modules, so any false non-equivalence will be avoided.

2.1.10 Partial reference netlist

2.1.10.1 Two steps ECO

In some design flows, a full chip synthesis may take too long time. To improve the turn-around time, only these modules involving ECO are re-synthesized. However the partial netlist can't directly apply to the implementation netlist. Since there maybe boundary optimization in the implementation netlist, partial netlist doesn't have full boundary information, so two steps ECO is used.

· Step 1. The partial new reference netlist is to fix the old full reference netlist. And new full reference netlist is generated by the partial netlist. 'set_mod2mod' is used to do module mapping.

· Step2. The new full reference is used to fix the implementation netlist.

2.1.10.2 Step 1. Use partial netlist to fix reference netlist

The pseudo-code is

read_library("art.90nm.lib"); # Read in standard library
read_design("-ref", "partial_reference.gv"); # Read in the partial Reference Netlist
# Read in the reference netlist under ECO
read_design("-imp", "reference.gv");
# Map 'smod' in partial netlist to 'smod' in the full netlist under ECO
set_mod2mod("smod", "smod");
set_top("smod");
fix_logic("state_reg_0_/D");
write_verilog("new_reference.gv");

2.1.10.3 Step2. Use the new reference netlist to fix implementation netlist

read_library("art.90nm.lib"); # Read in standard library
read_design("-ref", "new_reference.gv"); # Read in the partial Reference Netlist
# Read in the implementation netlist under ECO
read_design("-imp", "implementaion.gv");
set_top('smod');
fix_logic('state_reg_0_/D');
write_verilog("eco_implementation.gv");

2.2 Automatic Metal O nly ECO Flow

2.2.1 Overview

In Metal Only ECO, the design has completed place and route. Any new gates added should map to spare gates that located in the design.

Figure 5, Metal Only ECO

The flow can use internal synthesis engine to map patch logic to spare types. It requires one of the spare type combinations as the following

· Two ports 'and/or' gates and 'inv' gates, 'mux' is optional.

· Two ports 'nand/nor' gates and 'inv' gates, 'mux' is optional.

The flow can use external Synthesis Tool as well. The executable synthesis command should be in the search path. The supported Synthesis Tool is RTL Compiler from Cadence and Design Compiler from Synopsys.

A Design Exchange Format file is needed to map new instances to the closest spare gate instances. If DEF file is not loaded, GOF processes the ECO with gates type from the spare list without mapping to the exact spare instances. P&R tool like SOC Encounter will map the new instances in new netlist to the closest spare gates.

In 'fix_logic' command, GOF analyzes the non-equivalent points and optimize the logic cone to find the minimum gate count patch circuit. GOF writes out the patch in Verilog file and a TCL script for external Synthesis Tool if it's enabled. The TCL script is to constrain the Synthesis Tool to use spare gates only when remapping the gates in the patch file. The Synthesis Tool is run with the Verilog file and TCL script as inputs, and it writes out remapped Verilog patch file which has only spare gate types.

When the spare-only patch file is created, user can pause the flow by '-pause' in 'map_spare_cells' command. User can either modify the patch file manually or tunes up the constraint file to rerun the synthesis for several iterations until the patch netlist meets the requirement. Then press 'n' key to resume the flow.

GOF reads back the spare-only patch file and fits the circuit into the implementation netlist to fix the logic cones.

When ECO is done, a report can be created and ECO netlist/ECO script can be written out for the back end tool and LEC tool.

2.2.2 Files and data requirements

Standard library (Synopsys Liberty) files with extension '.lib'.
Other Verilog libraries if '.lib' files can’t cover.
Implementation Netlist.
Reference Netlist.
DEF (Design Exchange Format) file. It’s optional. If it is not loaded, GOF won’t map the spare gate type cells to the exact spare instances.
Spare gates pattern. It is in 'hierarchical_instance/leaf_instance' format. It has wild card '*' to match the spare gates in Implementation Netlist.
Spare gates list file. If several users work on the same Implementation Netlist, the initial spare gates list file should be generated only once. And new spare gates list file should be created every time an ECO is done.
The non-equivalent points report by LEC tool. They are either output ports or sequential cells’ input pins, E.G. 'dout', 'state_reg/D'.

2.2.3 Steps to do automatic Metal Only ECO

A typical situation for an automatic Metal Only ECO:

· Synthesize the new RTL to get Reference Netlist

· Run LEC on Reference Netlist to Implementation Netlist.

· Collect the failing points in the above run.

· Draft a GofCall script:

§ Load Standard Cell libraries and Verilog libraries.

§ Load the Reference Netlist and Implementation Netlist.

§ Specify the failing points in 'fix_logic' command.

§ Load DEF file, optional.

§ Load LEF file, optional. It's useful in LayoutViewer feature.

§ Create Spare Gates List by Spare Gates pattern or by reading in spare list file.

§ Run 'map_spare_cells' to remap the patch from 'fix_logic' command to all spare gates type patch netlist and select the closest spare instances for each gate in the patch netlist.

· Run the script which will call Synthesis Tool in the middle and create remapped patch file.

· Report ECO status and write out ECO results.

2.2.4 Example GofCall script for Metal Only ECO

The GofCall script has the exact same syntax of Perl script. But it can execute exported commands that access the netlist database and modify the netlist.

The following shows an example of an automatic Metal Only ECO:

# GofCall ECO script, run_metal_only_example.pl

use strict;

undo_eco; # Discard previous ECO operations

# Setup ECO name

setup_eco("eco_metalonly_example " );

read_library("art.90nm.lib"); # Read in standard library

read_design("-ref", "reference.gv"); # Read in the Reference Netlist

read_design("-imp", "implementation.gv"); # Read in the implementation Netlist Which is under ECO

set_top("topmod"); # Set the top module that ECO is working on

my @fixpoints; # Define the fix points

push @fixpoints, "state_reg_0_/D"; # Fill in the failing point reported from LEC tool

push @fixpoints, "state_reg_1_/D"; # Fill in the failing point reported from LEC tool

fix_logic(@fixpoints); # Execute fix_logic command to fix all the failing points

# The above is the same as all layers functional ECO

# The following is metal ECO related

read_def("topmod.def"); # Read Design Exchange Format file, optional

# Specify spare cell pattern, when 'map_spare_cells' is done, a new spare list file will be written out

# with updated spare list.

get_spare_cells("*/*_SPARE*");

# Comment the above line and use the following line to use spare list file

# if the spare list file has been generated already and gone through other ECOs

# get_spare_cells("-file", "spare_list_file.txt");

map_spare_cells();

# Use one of the following lines if external Synthesis Tool is used

# map_spare_cells ( "-syn", "rc" );

# map_spare_cells ( "-syn", "dc_shell" );

report_eco(); # ECO report

write_verilog("eco_verilog.v"); # Write out ECO result in Verilog

write_soce("eco_soce.tcl"); # Write out TCL script for SOC Encounter

exit; # Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.2.5 Run and debug

The GofCall Script can be run by '-run' option.

gof -run run_metal_only_example.pl

User can insert 'die' command to let GOF stop in some point and do interactive debugs when ‘GOF >’ shell appears. GUI mode can be enabled by run 'start_gui' command.

'report_spare' can tells what types of spare gates and how many numbers are available. User can check if the failing point has been fixed as expected by bring up a schematic in ECO mode. It can be done by insert 'sch' command

…

report_spare;

my @fixpoints;

push @fixpoints, "state_reg_0_/D";

push @fixpoints, "state_reg_1_/D";

fix_logic(@fixpoints);

sch("state_reg_0_");

…

For the full APIs/Commands list, run 'help' in the GOF shell.

See Run and debug GofCall script section for more detail

2.3 Automatic Setup Timi ng ECO Flow

2.3.1 Overview

GOF supports setup timing fix by swapping low speed gates to high speed gates. A Primetime report file is needed in this flow. GOF analyzes the report file and creates weight for each path and each instance. The fix is started from the most critical instance in the most critical path.

For example, the following diagram shows three violation paths. S0 to E0 has -0.5 slack. S1 to E1 has -0.9 slack. And S2 to E2 has -0.3.

Figure 6 Violation paths and bottleneck

Instance B0 has all three paths passing through, and it has heaviest weight 1.7.

GOF starts from path S1 to E1 and fixes B0/C0/A1/D1/A0/D0/A2/D2 in sequence. If swapping B0 to higher speed gate can speed up 1.0, then all violations are fixed by swapping B0. If B0 save is 0.7, then path S0->E0 and S2->E2 are fixed. Swapping C0 to save 0.2 would fix S1->E1 as well.

2.3.2 Files and data requirements

Standard library (Synopsys Liberty) files with extension '.lib'.
Other Verilog libraries if '.lib' files can’t cover.
Implementation Netlist.
Prime-time setup timing report file.

Report : timing

-path_type full_clock_expanded

-delay_type max

-input_pins

-nets

-slack_lesser_than 0.5000

-max_paths 10000

-transition_time

-capacitance

2.3.3 Steps to do setup fix

Run Prime-time setup timing report on Implementation Netlist.
Draft GofCall script:

Load Standard Cell libraries and Verilog libraries.
Load Implementation Netlist.
Load setup timing report file.
Add 'fix_setup' command.

Run the script.
Report ECO status and write out ECO results.

2.3.4 Sample code

# Fix setup timing, fix_setup_timing.pl

use strict;

undo_eco;

setup_eco("setup_eco0123");

set_log_file("setup_eco0123.log");

read_library("/lib/tsmc/tsmc40.hvt.lib");

read_library("/lib/tsmcr/tsmc40.rvt.lib");

read_design('-imp', "/prj/netlist/rtc_gen.gv");

read_file("-format", "pt", "/prj/pt/rpt/pt_max.report");

set_top("rtc_gen"); # The module level that timing would be fixed

fix_setup("-margin", 0); # Final slack will be larger than 0

report_eco();

write_verilog("setup_eco.v");

2.3.5 Run and debug

The GofCall Script can be run by '-run' option.

gof -run fix_setup_timing.pl

Check Run and debug GofCall script section for more detail

2.4 Automatic Hold Timi ng ECO Flow

2.4.1 Overview

GOF supports hold timing fix by inserting delay/buffer gates. A Primetime report file is needed in this flow. Same as the Automatic Setup Timing fix flow, GOF analyzes the report file and creates weight for each path and each instance. The fix is started from the most critical instance in the most critical path by inserting Delay/Buffer gates.

2.4.2 Files and data requirements

Standard library (Synopsys Liberty) files with extension '.lib'.
Other Verilog libraries if '.lib' files can’t cover.
Implementation Netlist.
Primetime hold timing report file.

Report : timing

-path_type full_clock_expanded

-delay_type min

-input_pins

-nets

-slack_lesser_than 0.5000

-max_paths 10000

-transition_time

-capacitance

2.4.3 Steps to do hold fix

Run Primetime hold timing report on Implementation Netlist.
Draft GofCall script:

1. Load Standard Cell libraries and Verilog libraries.

2. Load Implementation Netlist.

3. Load hold timing report file.

4. Add 'fix_hold' command.

Run the script.
Report ECO status and write out ECO results.

2.4.4 Sample code

# Fix hold timing, fix_hold_timing.pl

use strict;

undo_eco;

setup_eco("hold_eco0123");

set_log_file("hold_eco0123.log");

read_library("/lib/tsmc/tsmc40.hvt.lib");

read_library("/lib/tsmcr/tsmc40.rvt.lib");

read_design('-imp', "/prj/netlist/rtc_gen.gv");

read_file("-format", "pt", "/prj/pt/rpt/pt_min.report");

set_top("rtc_gen");

fix_hold("-buffer", "DLY2_X4_HVT", "-margin", 0); # Final slack will be larger than 0

report_eco();

write_verilog("hold_eco.v");

2.4.5 Run and debug

The GofCall Script can be run by ‘-run’ option.

gof -run fix_hold_timing.pl

Check Run and debug GofCall script section for more detail

2.5 Script Mode Manual EC O Flow

2.5.1 Overview

In many cases, the ECO operations are well known by users. They can be inserting buffers to a 128bits bus, or adding isolation AND gates to all outputs of a module. In these cases, manual ECO by scripts is more efficient and resource saving.

GOF exports many APIs for ECO operations in GofCall script.

2.5.2 Steps to do Manual ECO In Scripts

A typical situation for a Manual ECO:

· Run LEC on modified RTL to Implementation Netlist.

· Collect the failing points in the above run.

· Draft a GofCall script:

§ Define ECO name in ‘setup_eco’.

§ Load Standard Cell libraries and Verilog libraries.

§ Load Implementation Netlist.

§ Locate ECO point.

§ Use ECO APIs to fix the logic.

· Run the script.

· Report ECO status and write out ECO results.

2.5.3 Locate ECO point

Locating ECO point is the hardest part in manual ECO. Wire names in RTL codes are normally optimized away by synthesis process. GOF has a feature to retrieve the nets. Check here for the GUI way or use API ' get_match_nets' in GofCall script.

2.5.4 Files and data requirements

Standard library (Synopsys Liberty) files with extension ‘.lib’.
Other Verilog libraries.
Implementation Netlist.
ECO locations.

2.5.5 ECO APIs list

These APIs change the implementation netlist

· change_pin: Modify pin connection in ECO.

· change_gate: Modify an instance type in ECO.

· change_net: Change an existing net's driver.

· change_port: Change an output port's driver.

· new_net: Create a new net.

· new_gate: Create a new gate instance.

· new_port: Create a new port.

· del_net: Delete a net.

· del_gate: Delete a gate.

· del_port: Delete a port.

For the full list of the APIs, user can type 'help' in 'GOF >' shell.

For the individual API, type 'help api_name' . For example:

GOF > help new_port

Help for new_port

new_port: ECO command. Create a new port for the current top level module

ECO command. Create a new port for the current top level module

Usage: new_port($name, @options);

$name: Port name

@options:

-input: New an input port

-output: New an output port

-inout: New an inout port

Note: The port name has to be pure words or with bus bit, like, abc[0], abc[1]

Examples:

new_port('prop_control_en', '-input'); # create an input port naming 'prop_control_en'

new_port('prop_state[2]', '-output'); # create an output port with bus bit 'prop_state[2]'

new_port('prop_state[3]', '-output'); # create an output port with bus bit 'prop_state[3]'

2.5.6 Example GofCall script for Manual ECO

# GofCall ECO script, run_example.pl

use strict;

undo_eco; # Discard previous ECO operations

setup_eco("eco_example"); # Setup ECO name

read_library("art.90nm.lib"); # Read in standard library

read_design("-ref", "reference.gv"); # Read in Reference Netlist

read_design("-imp", "implementation.gv"); # Read in implementation Netlist Which is under ECO

set_top("topmod"); # Set the scope to the module that ECO is working on

# The following API adds a mux in flop 'state_reg_0_' D input pin,

# and connect up the original connection to pin 'A',

# pin 'B' connect to net 'next_state[7]', and pin 'S' to net 'sel_mode'

# the net can be replaced by format of 'instance/pin' , E.G. '.S(state_reg_2_/Q)'

change_pin("state_reg_0_/D", "MX2X4", "", ".A(-),.B(next_state[7]),.S0(sel_mode)");

report_eco();

write_verilog("eco_verilog.v"); # Write out ECO result in Verilog

write_soce("eco_soce.tcl"); # Write out TCL script for SOC Encounter

exit; # Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.5.7 Run and debug

Check Run and debug GofCall script section for more detail

2.5.8 Handle repetitive work

A Perl 'for' or 'foreach' loop can handle repetitive work efficiently. For example, to add a 'AND' isolation gate for every output port of a module.

# GofCall ECO script, add_ands.pl

use strict;

undo_eco; # Discard previous ECO operations

setup_eco("eco_example"); # Setup ECO name

read_library("art.90nm.lib"); # Read in standard library

read_design("-ref", "reference.gv"); # Read in Reference Netlist

read_design("-imp", "implementation.gv"); # Read in implementation Netlist which is under ECO

set_top("topmod"); # Set the top module that ECO is working on

my @ports = get_ports("-output"); # Get all output ports of module 'topmod'

# For each output port of 'topmod', insert an 'AND' gate to enable it only when 'enable_out' is high

foreach my $port (@ports){

change_port($port, "AND2X2", "", "-,enable_out");

}

report_eco();

write_verilog("eco_verilog.v"); # Write out ECO result in Verilog

write_soce("eco_soce.tcl"); # Write out TCL script for SOC Encounter

gexit; # Exit when the ECO is done, comment it out to go to interactive mode when ’GOF >’ appears

2.5.9 Special character

The special character '-' is used to represent existing connection. For example

change_pin("U0/A", "BUFFX1", "eco_buf", "-");

A buffer is inserted into A pin of instance U0. The old existing net drives the new buffer now.

The special character '.' is used in ECO new instance name if the new instance needs to be in the same hierarchy as the ECO spot.

change_pin("u_qcif/u_num2/u_spare1/B", "AOI21X2", ".", "net1,net2,net3");

If the instance is empty, GOF creates 'AOI21X2' in the current top level. With ".", GOF creates 'AOI21X2' new instance in hierarchy "u_qcif/u_num2/u_spare1".

2.6 Script Mode Manual Metal Only EC O Flow

2.6.1 Overview

In Manual Metal Only ECO, any new added gates will be automatically mapped to spare gate instances by 'map_spare_cells' command. A Design Exchange Format file has to be loaded for the tool to find optimal spare instances. If the file is not present, the mapping is skipped.

2.6.2 Files and data requirements

Standard library (Synopsys Liberty) files with extension '.'lib'.
Other Verilog libraries.
Implementation Netlist.
DEF (Design Exchange Format) file. If it is not loaded, GOF won’t map the spare gate type cells to the exact spare instances.
Spare gates pattern. It is in ‘hierarchical_instance/leaf_instance’ format. It has wild card '*' to match the spare gates in the Implementation Netlist.
Spare gates list file. If several users work on the same Implementation Netlist, the initial spare gates list file should be generated only once. And a new spare gates list file should be created every time ECO is done.
ECO locations.

2.6.3 Example GofCall script for Manual Metal Only ECO

# Manual Metal Only ECO, manual_metal_eco.pl

use strict;

undo_eco;

setup_eco("metal_eco0123");

set_log_file("metal_eco0123.log");

read_library("/prj/lib/tsmc40.lib");

read_design("-imp", "/prj/netlist/imp_net.v");

set_top("mtop");

new_port("nout7", "-output"); # Create a new port 'nout7'

# Place the port to 60000, 1000000. It's approximate position, the main purpose is for

# spare instances selection

place_port("nout7", 60000, 100000);

new_port("nout8", "-output"); # Create another port

place_port("nout8", 120000, 81000);

# 'nout8' is driven by an invert first, and the invert's input is driven by pin 'cmpmod/rego/QN'

change_port("nout8", "INV_X1M", "", "cmpmod/rego/QN");

# Drive the 'nout7' by 'INV_X1M' and leave the input unconnected, but the mapped

# spare instance name is returned.

my $inst = change_port("nout7", "INV_X1M", "", "");

# Drive the new instance's input by a flop, and specify the flop's connection in the 4^th argument

change_pin("$inst/A", "SDFFRPQ_X4M", "", ".CK(cmpmod/rego/CK),.D(cmpmod/rego/QN),.R(1'b0),.SE(1'b0),.SI(1'b0)");

read_def("/prj/def/imp_net.def");

get_spare_cells("Spare_*/*_SPARE_GATE*");

# The following 'map_spare_cells' command maps the three new ECO instances to the optimal

# spare instances.

map_spare_cells;

report_eco;

write_verilog("imp_eco0123.v");

2.6.4 Run and debug

The GofCall Script can be run by ‘-run’ option.

gof -run manual_metal_eco.pl

Check Run and debug GofCall script section for more detail

2.7 GUI Mode Manual ECO Flow

2.7.1 Overview

The following paragraph demonstrates how to insert buffers and inverters into timing path in GUI mode.

2.7.2 Start up GOF in GUI Mode

Start up Gates On the Fly by the command line

gof -lib t65nm.lib -lib io.lib netlist_port.v

For detail usage, visit this link

http://www.nandigits.com/usage.htm

In GofViewer netlist window, press ctrl-g or menu commands->’Launch GofTrace with gate’. Fill in the instance name that needs ECO.

Figure 7 Load gate to schematic

2.7.3 Create Partial Schematic

In GofTrace schematic window, use mouse middle button to expand the schematic. In this case, pin D of the flop should be inserted an invert.

Figure 8 Partial Schematic for GUI ECO

2.7.4 Do ECO on schematic

Check ECO button to enable ECO mode

Figure 9 Schematic in ECO Mode

Press mouse-left-button on the wire to select it. Click ECO button ‘Insert gates into connections’, select the right invert in the gate type selection window.

Figure 10 Select Gate in GUI ECO

In ‘Pin Connections’ setup window, use default ‘Complete Loop’ option, so that the gate can be inserted in the net.

Figure 11 New Cell Pin Connection Selections

Click OK and the invert is inserted.

Figure 12 Manual ECO with New Gate Inserted

2.7.5 Save ECO

Press ECO button ‘Save ECO result to file’. And select the format to be saved. The supported formats include verilog netlist, SOC Encounter ECO script, GofCall Script, TCL script and DCShell script.

Figure 13 Save ECO in GUI Mode

2.8 GUI Mode Manual Metal Only ECO Flow

2.8.1 Overview

Metal ECO can only use existing gates on the silicon. User has to check the layout physical position to find the best gates. In Manual Metal ECO the spare cell has to be located first, or there may be no exact cell (an invert for example) close by at all and it has to be converted by other gates. The following paragraph demonstrates how to use GOF’s layout viewer to find the proper invert and use GOF’s GUI ECO to add the gate.

2.8.2 Start up Gates On the Fly in GUI mode

GOF should be started up by loading lef and def files in order to view the layout.

gof -lib t65nm.lib -lib io.lib netlist_port.v -lef t65nm.lef io.lef -def top.def

For detail command line usage, visit this link

http://www.nandigits.com/usage.htm

In GofViewer netlist window, press ctrl-g (Press both 'Ctrl' key and 'g' key) or menu commands->’Launch GofTrace with gate’. Fill in the instance name that needs ECO.

Figure 14 Load Gate to Schematic in Metal Only ECO

2.8.3 Analyze the partial schematic

Use mouse-middle-button to expand the schematic. Use mouse-left-button or press ctrl-a to select all the schematic. Press mouse-right-button to select menu ‘Copy selected to->Layout New’

Figure 15 Schematic Interactive to Layout Viewer

On the layout viewer, the partial schematic/circuit is shown by points and arrow wires. In the search entry at the bottom, enter ‘*spare*’ and press ‘Enter’ key to high light all spare gates close to the circuit. The high lighted spare gates are in green. The spare string can vary depending on the implementation.

Figure 16 Layout Viewer Window

Now the goal is to find an invert near the blue high lighted circuit and insert it into the connection.

· Press ‘Shift’ key and don’t release.

· Use mouse-left-button to draw a virtual rectangle on the layout viewer window.

· Release mouse-left-button and ‘Shift’ key.

· All the spare gates inside the virtual rectangle have their out-lines high lighted.

· Use mouse- right-button to pop menu.

· Select command ‘Copy Selected to->Schematic #’ to send the selected spare gates back to the schematic under ECO.

Figure 17 Mouse and Key Operations to Select Multiple Spare Gates

2.8.4 Implement ECO on the schematic

Now the candidate spare gates are all on the schematic. Check all the gate types, and invert can’t be found. But the invert logic can be implemented by tying two inputs pin of NAND gate.

Figure 18 Load Spare Gates on Schematic

Since there are two NAND gates, more interactions can be done between the schematic and layout viewer to find the best closest NAND gate.

Figure 19 Schematic and Layout Viewer Interactive

By checking different color on Layout Viewer (Select color bar), the two NAND gates are displayed in different colors. The NAND gate in red solid point appears more close to the circuit under ECO. So that NAND is selected to be inserted in the connection.

Figure 20 Spare Gates Shown in Different Colors on Layout Viewer

Move the NAND gate closer to the circuit on the schematic. Check ‘ECO’ button to enable ECO mode. Use mouse-middle-button to trace the input pins of the NAND gate, since they tied to zeros in the netlist.

Figure 21 Enable ECO Mode

To select all the connections to be deleted:

· Press ‘Ctrl’ key and don’t release.

· Use mouse-left-button to click on the wires.

Click ‘Delete selected item’ ECO button to delete the selected wires.

Figure 22 Do ECO on Schematic

To connect up the new connections:

· Press mouse-middle-button on one of the empty input pins and don’t release.

· Move cursor to the destination output pin.

· Release mouse-middle-button.

· The connection is created.

· The hierarchical connectors are added if the source and destination pins are in different hierarchies.

Figure 23 Ports are automatically added

2.8.5 Save ECO

Figure 24 Save ECO in Metal Only

3 Guideline to choose Netlist ECO flows

3.1 Overview

ECO cases vary in complexity. It can be as simple as one cut or adding one gate and it can be as complicated as involving thousands gates.

3.2 Decision Factors

1. Timing or functional

§ Timing ECO up-sizes or down-sizes cells, buffers or inverters can be added or deleted. It doesn't change netlist functionality.

§ Functional ECO involves function changes.

2. Metal only or full layers

§ Metal only ECO changes metal layers, any new gates should use spare gates.

§ Full layers ECO can modify netlist freely.

3. Close to flops or ports or instances with name preserved

§ When ECO spot is close to flops or ports or instances with name preserved, wire and instance names will be kept the same as the RTL. Manually modification becomes possible.

§ The change in RTL is on some combinational wires which may have been optimized away or may have different functionality in netlist even with the same name. Automatic ECO with reference netlist is recommended in this case.

4. Random or Repeated

§ Random ECO can be in any location of the netlist. Multiple spots in the netlist may have to be modified with different operations.

§ Repeated ECO does same operations on a group of wires/ports/instances, for example, adding AND gates to all output ports for one module. It is more efficient to do these ECOs in manual script mode.

5. Involving more than 50 gates

§ ECO involving more than 50 gates becomes hard for manually modification and if the change is not repeated and not close to flops and ports, automatic should be chosen. However, this threshold number depends on users, it can be increased or decreased.

§ When ECO has less than the threshold gate number and the ECO spot is close to flops and ports, manually modification becomes feasible.

6. GUI or script mode

§ GUI mode is easier to ramp up. For users not doing ECO frequently, GUI mode is a good choice.

§ Script mode is very powerful and efficient, and it's reproducible. When the ECO is repeated operations, script mode is preferred.

3.3 ECO flows decision tree

The ECO flows decision tree is illustrated in the diagram below:

Figure 25 ECO Flow Decision Tree

4 Script Mode Detail Features

4.1 GofCall Script

GofCall is the Perl Script Interface which can access internal exported APIs.

4.1.1 Get Help

Type 'help' in interactive shell 'GOF >' to list all APIs.
Type 'help set_*' to list all APIs matching 'set_', like 'set_top', 'set_invert'
Type 'help individual-API' to list detail of the API.
Visit www.nandigits.com/gof_manual.htm for online manual.

4.1.2 Features list

Compatible with Perl.
Automatic ECO with 'fix_logic'/'fix_setup'/'fix_hold' APIs.
Multiple ECO APIs to do manual ECO.
ECOs are reversible.
The result can be loaded in schematic on the fly.
Integrated commands to browser netlist and check design status

4.1.3 APIs list

buffer: ECO command. Buffer high fanout ECO nets

change_gate: ECO command. Modify an instance in ECO

change_net: ECO command. Change a exsiting net's driver

change_pin: ECO command. Modify pin connection in ECO.

change_port: ECO command. Change an output port's driver

check_design: Check if the design has unresolved modules or other errors

del_gate: ECO command. Delete gate

del_net: ECO command. Delete net

del_port: ECO command. Delete port

exist_inst: Check if an instance exists

exist_wire: Check if exist the wire

fix_hold: ECO command. Fix hold time violations

fix_logic: ECO command. Fix Implementation Netlist logic by Reference Netlist

fix_setup: ECO command. Fix setup time violations

get_cell_info: Get information of a module or instance

get_cells: Get all cells in the current module or and sub-modules

get_conns: Get connections of net or pin in the top level module

get_coord: Get cell's coordination

get_def: Get instantiation of instance

get_driver: Get the driver of a net or pin

get_drivers: Get the drivers of a net or pin

get_instances: Get all hierarchical instances in the top level module

get_leaf_pin_dir: Get leaf cell pin's direction input/output/inout

get_leafs_count: Get all leaf cells name and count in the top level module

get_lib_cells: Get leaf gates in libraries

get_logic_cone: Get logic cone of nets or pins

get_modules: Get all hierarchical modules under current module

get_net_of: Get the net name connecting to the pin

get_nets: Get nets that matching pattern

get_path: Get current hierarchical path

get_pins: Get pins of instance or module

get_ports: Get all ports in the current top level module

get_ref: Get the reference of the instance

get_resolved: Resolve the relative path to module and leaf item

get_roots: Get root designs name

get_spare_cells: ECO command. Get spare cells

gexit: Exit the GofCall interactive mode

gprint: Print out the message and save to log file

is_leaf: Check if a module or instance is leaf cell

is_seq: Check if a leaf module is a specific sequencial cell

map_spare_cells: ECO command. Map all new created cells to spare cells

new_gate: ECO command. Create new gate

new_net: ECO command. Create a new net

new_port: ECO command. Create a new port for the current top level module

place_gate: ECO command. Place gate position

place_port: ECO command. Place port position

pop_top: Pop out the saved top level module from the stack and discard current setting

push_top: Set the current top level module and push the previous setting to stack

read_def: Read DEF file

read_design: Read design

read_file: Read timing violation report file

read_lef: Read LEF file

read_library: Read stardard library

rename_net: ECO command. Rename a net name

report_eco: Report ECO

report_spares: Report Spare cells

run: Run GofCall script

sch: Launch schematic to verify ECO

set_exit_on_error: If the script encounters errors, exit the program.

set_invert: Set invert

set_keep_format: Set keep format of the original verilog when ECO is done

set_leaf: Set a hierarchical module to be leaf. The command is useful in saving the design in verilog file

set_log_file: Set log file name

set_max_lines: Set max output lines

set_max_loop: Setup max loop

set_mu: MU configuration

set_power: Set power pins connections for leaf cell

set_quiet: Run script in quiet mode

set_tiehi_net: Set tiehi net name

set_tielo_net: Set tielo net name

set_top: Set the current top level module

set_tree: Set the current tree

set_verbose: Run script in verbose mode

setup_eco: ECO command. Setup ECO

start_gui: Start GUI windows

stitch_scan_chain: ECO command. Stitch scan chain

undo_eco: ECO command. Undo eco operations

write_dcsh: ECO command. Write out ECO result in Design Compiler dcsh script format

write_soce: ECO command. Write out ECO result in Cadence SOC Encounter script format

write_spare_file: ECO command. Write out spare cells list file

write_tcl: ECO command. Write out ECO result in Design Compiler tcl script format

write_verilog: ECO command. Write out ECOed netlist to a file

For detail of each API usage visit

http://www.nandigits.com/gofcall_apis.htm

4.2 String Handling In Script Mode

4.2.1 Single quote and double quote

Any string in GofCall script for module/instance/wire/pin/port should be enclosed by single quote or double quote. When a Perl variable is used, double quote should be used

my $inst = "state_reg_0";

change_pin("$inst/D", "1'b0");

4.2.2 Instance and net with backslash

Instance with backslash should be either put in single quote and with a space in the end, or removed the backslash and let the tool to figure out the real name.

'\u_abc/u_def/state_reg[0] ' can be written as 'u_abc/u_def/reg_state_0[0]'

Net name with backslash should always keep the backslash. The good way to avoid write net name directly is to use 'instance/pin' format. For example

DFFQ_X4M \u_abc/u_def/state_reg[0] (.D(\u_abc/u_def/net123 ), .Q(\u_abc/u_def/state[0] ));

The net '\u_abc/u_def/net123 ' can be replaced by 'u_abc/u_def/state_reg[0]/D' and

The net '\u_abc/u_def/state[0] ' can be replaced by 'u_abc/u_def/state_reg[0]/Q'

4.3 Run and debug GofCall script

4.3.1 Command line

In command line, the GofCall Script can be run by ‘-run’ option.

gof -run run_example.pl

4.3.2 GOF Shell

If '-run' option is present in the command line, and 'gexit' is not in the script, or GOF meets error when executing the script, GOF goes to interactive mode with GOF shell 'GOF >'.

GofCall, Netlist Processing Script APIs, Interactive Mode

Run 'start_gui' to launch GUI window

Run 'help' to list API calls

GOF >

Individual command can be executed in GOF shell. The command can be in nested mode

GOF > set_top(get_ref("u_rxbuf"))

4.3.3 Run in GUI mode

GofCall scripts can be run in GUI window. In GofViewer, click Menu Commands->’Launch GofCall Script Interface’ to launch GofCall GUI window.

Type ‘help’ in the shell entry for help information. Scripts can be run by ‘run’ command in the shell entry

Figure 26 GofCall window

4.3.4 Fast schematic launch

In GOF shell, GUI windows can be launched by 'start_gui' or 'sch' commands.

'start_gui' launches netlist view window first and user can bring up schematic window from netlist view window.

'sch' command only launches schematic window, and it doesn't enable netlist view window. So it has fast turnaround in GUI interactive debug.

For example,

After the following command is done,

change_pin("u_top/u_core/u_regmod/state_reg/D", "XOR2X2", "", "-,new_enable");

Run 'sch' in 'GOF >'

GOF > sch("u_top/u_core/u_regmod/state_reg")

The instance will be loaded into a schematic and user can click on the instance's pins to trace fanin/fanout on the schematic to see if the ECO is done as expected.

4.3.5 Break points for debug

'sch' fast schematic launch command can be used as break points for debug. For example, 'sch' commands are inserted in GofCall script, when the tool runs to the point, a schematic is launched.

…

setup_eco("sanity75");

set_log_file("t_sanity75.log");

read_library("libdr/art.m.simple.lib");

read_design('-imp', "cdir/imp_name.v");

change_pin("state_reg_0_/D", "MX2X4", "", ".A(-),.B(next_state[7]),.S0(sel_mode)");

sch("state_reg_0_", "-set", 1);

…

On the schematic, user can use mouse-middle-button clicking on the pin 'D' to see if the ECO is done as expected.

Figure 27 Launch schematic at break point

Note: 'ECO' check-button is enabled automatically, since there is ECO having been done.

To compare with the logic before ECO, launch a new schematic by menu Schematic->'New Schematic'. On the new schematic, press 'ctrl-g' or by menu Schematic->'Load Gate' to load in the flop under ECO.

Figure 28 Launch schematic before ECO

Note: 'ECO' check-button is un-checked.

5 GUI Mode Detail Features

5.1 GofViewer

When GOF is run without '-run' and '-shell' option, it goes into GUI mode.

GofViewer is the first window after GOF starts up GUI interface.

Figure 29: GofViewer Window

5.2 Log Window

If there errors or warnings in loading the database, Log Window pops up

Figure 30: Log Window

5.2.1 File Menu

5.2.1.1 Load Design

Users can input netlist files and design files through the Load Design command.

5.2.1.2 Reload Design

If any netlist file or design file has been updated during GOF session, this command can be used to reload the design.

5.2.1.3 Save Startup File

This command saves the inputs users have typed in Load Design window to startup file. In Windows platform, it’s a batch file with ‘bat’ extension. In Linux platform, it’s a shell file. Users can load the design by running the startup file in the next time.

5.2.1.4 Open Other Netlist

This command loads another netlist file to create a new hierarchical tree. The hierarchy tree will be listed in the hierarchy list window. The command is useful when users want to draw circuits from different netlist file on the same schematic which is good for logic comparison in netlist debug scenario such as LEC failures analysis.

5.2.1.5 Open Log Window

The command opens log file in a text window.

5.2.1.6 Exit

Exit command.

5.2.2 Find Menu

5.2.2.1 Search

This command searches for the matching string in the netlist text window.

5.2.2.2 Goto Line Number

GOF loads only one module in the netlist text window when the netlist file is hierarchical with multiple modules. The command will load in the corresponding module into the text window and highlight the line with the specific number in the netlist file.

5.2.2.3 Report Area

This command reports the design area. The command requires standard library files to be loaded which include leaf cell area information.

5.2.2.4 Report Leakage

This command reports the leakage power in the design. Same as the Report Area command it requires standard libraries.

5.2.2.5 Report Leaf Cells

This command reports the leaf cell type and numbers in the design.

5.2.2.6 Report Submodules

This command reports the hierarchical sub-modules in the design.

5.2.2.7 Statistic of Current Design

This command reports the statistic of the current design. It pops up an option window for interactivity from users.

5.2.2.8 List Library

The command lists the libraries and leaf cells in each library.

5.2.2.9 List Context for Leaf Cell

This command pops up an entry window for users to input leaf cell name string, wild card can be accepted. All leaf cells matching the string will be listed. If there is only one cell matched, the detail property will be listed.

5.2.3 Commands Menu

5.2.3.1 Launch GofTrace Schematic

This command launches GofTrace Schematic, if any instance or net string is highlighted in the netlist window, the instance or the driver of the net will be drawn on the schematic. Otherwise, the schematic is empty.

5.2.3.2 Launch GofTrace with Gate

This command pops up an entry window for users to input a string to load a specific instance. For example, ‘u_abc/U123’. Click ‘OK’ button on the pop window, GofTrace Schematic is launched.

5.2.3.3 Launch Layout Viewer

This command launches Layout Viewer window, if any instance or net string is highlighted in the netlist window, the instance or the driver of the net will be highlighted on the Layout Viewer window. The command requires that physical files to be loaded. Both def and lef files should be loaded before launching Layout Viewer, otherwise a warning window pops up for the missing physical files.

5.2.3.4 Launch GofCall Script Interface

This command launches GofCall window to run scripts or other interactive command.

5.2.3.5 Switch to GOF Shell Mode

This command exits GUI mode and switches to shell mode. It has ‘GOF >’ shell interface in shell mode.

5.2.3.6 Spare Cells

This command group processes Spare cells in metal ECO. Warning! GUI metal ECO is used for visually check the possibility of metal ECO. The script mode metal ECO is recommended.

5.2.3.6.1 Create Spare Cells File

This command extracts spare cells from netlist file. It requires that spare instances name complies name convention specified in Menu Setup->GofECO->Setup->SpareCellPattern. The default is ‘spare_\w+_\d+’ . If multiple users are doing different ECO at the same time, the spare cells file should be stored in a public directory that all users can access, so that users won’t reuse a spare cell already used in one ECO.

5.2.3.6.2 Load Spare Cells File

This command loads in the spare cells file created by the above command.

5.2.3.7 Launch Files Compare Window

This command launches netlist files compare window. The netlist compare function can do more than simple Linux ‘diff’ command.

5.2.3.8 Process Timing Violations

This command processes Prime Time report file. Read this PDF file for the use case.

www.nandigits.com/use_cases/gof_timing_analysis.pdf

5.2.3.9 SDF

This command group processes SDF file for delay information interactivity.

5.2.3.9.1 Create SDF Index File

GOF reads in SDF Index File instead of SDF file itself, since SDF can have huge size. Once the index file is created it can be reused next time and loaded in much faster.

5.2.3.9.2 Load SDF Index File

This command loads in already created SDF Index File.

5.2.4 Options Menu

5.2.4.1 Hierarchy Window Font

Check GofViewer Figure for the hierarchy list window position

5.2.4.1.1 Increase Font Size

Increase font size in the hierarchy list window.

5.2.4.1.2 Decrease Font Size

Decrease font size in the hierarchy list window.

5.2.4.2 Netlist Window Font

Netlist window locates in the right side of GofViewer window. Check GofViewer Figure for the netlist text window position

5.2.4.2.1 Increase Font Size

Increase the font size in netlist window.

5.2.4.2.2 Decrease Font Size

Decrease font size in netlist window.

5.2.4.3 Dump Waveform Restore File

An option window pops up for users to choose which dump restore file to be saved. It’s useful for netlist simulation debug. When one format box is checked, in pop menu, ‘Write Waveform Restore File’ item is presented on the top when one net is selected in the netlist window.

5.2.4.4 Setup

Integration of various setup information.

5.2.5 Help Menu

5.2.5.1 General

General help information.

5.2.5.2 About

About Gates On the Fly.

5.2.5.3 nandigits.com/gof_manual.htm

Visit the website for this manual.

5.2.5.4 Read Ethernet Mac Address

Read out MAC address. When users decide to purchase licenses or ask for evaluation licenses, MAC address is required to generate GOF licenses.

5.2.6 Keyboard Shortcuts

5.2.6.1 Access Menu

Press key ‘Alt’ and underlined letter in menu.

5.2.6.2 Functions access

· Ctrl-a: Select all text lines

· Ctrl-c: Copy the marked (highlighted) string

· Ctrl-v: Paste the content in clipboard

· Ctrl-d: Trace driver of the marked net

· Ctrl-f : Search function

· Ctrl-g: Load instance to schematic

· Ctrl-s: Emacs style search forward

· Ctrl-r: Emacs style search backward

· Ctrl-w: Write to waveform dump restore file

· Ctrl-x: Exit the current window

5.2.7 Selection Status

Click mouse-left-button on netlist text window, the object which can be net, instance or module under the cursor is highlighted. Netlist window pop menu has different content according to the selection status. Pressing keys Ctrl-a can have all content in the netlist window selected. Press mouse-left-button and don’t release, move mouse down to select multiple lines.

5.2.8 Netlist Window Pop Menu

Click mouse-right-button and release, a pop menu appears under the cursor. The menu content varies with the selection status in the netlist window.

5.2.8.1 Search

Search for a string in the netlist window. Keyboard shortcut is Ctrl-f.

5.2.8.2 Copy Selected to

Copy the selected object (net or instance) to new schematic window or existing schematic window.

5.2.8.2.1 Schematic New

Copy the selected object to a new schematic.

5.2.8.2.2 Schematic #number

Copy the selected object to an existing schematic window.

5.2.8.3 Driver of the selected net

Trace to the driver of the selected net. The netlist window will show the instance that drives the net and mark the driven net.

5.2.8.4 List Connectivity of the selected net

Pop up a window to list the connectivity of the selected net.

5.2.8.5 List Fanin EndPoints

Pop up a window to list the fanin endpoints including flops and input ports that drive the selected net.

5.2.8.6 List Fanout EndPoints

Pop up a window to list the fanout endpoints including flops and output ports that are driven by the selected net.

5.2.8.7 Parent Module

Go to the definition location of the parent module calling the current module. It’s only active in sub-modules, not in root top level module.

5.2.8.8 List Context

List the context of the selected object which can be net, instance or module.

5.2.9 Hierarchy Window Pop Menu

Click mouse-right-button and release, a pop menu appears under the cursor. The menu content varies with the selection status in the hierarchy window.

5.2.9.1 Run Custom Command: Command Name

It requires users to setup the custom command in menu Options->Setup->Misc->’Custom command’. The command can be a editor application, such as ‘emacs’. It opens the netlist file with the editor.

5.2.9.2 Show Definition

Open the module content and display it in the netlist window.

5.2.9.3 Show Calling

Open the parent module and highlight the instantiation location.

5.2.9.9 Edit Module of the selected design

Edit the module by using edit tool defined in menu Options->Setup->Misc->’Edit tool’. It will ask for a directory for storing temporary files.

5.2.9.10 Save Module of the selected design

After editing, the edited modules can be saved into a file.

5.2.9.11 Goto Line Number#

See Goto Line Number

5.3 GofTrace

GofTrace is an incremental schematic engine. Users control how to expand the schematic by clicking the input/output pins of gates with mouse-middle-button. Users can adjust the positions of the gates on the schematic any time by mouse-left-button.

Figure 31: GofTrace Window

5.3.1 5.3.2 Mouse buttons usage

5.3.2.1 Mouse Left Button

Mouse left button is used to select object. Click on any object, it is highlighted to indicated being selected. Press 'ctrl' key and clock on objects to select multiple objects. Press the button and move the mouse to select multiple objects at one time.

5.3.2.2 Mouse Middle Button

Mouse middle button is used to trace the schematic. Click on input/output pins to expand the schematic. It used to do drag-drop function as well. In ECO mode, it's used to connect floating input pin to existing nets.

5.3.2.3 Mouse Right Button

Mouse right button is to popup menu.

5.3.3 File Menu

5.3.3.1 Save

Save the schematic to a file for future usage. The saved file has extension ‘.st’ which can only be used by GOF in ‘Open’ schematic command shown below.

5.3.3.2 Open

Open schematic stored by Save command above.

5.3.3.3 Print

Print schematic to a printer or file. Printer Page Setup window pops up for the print scope setup. In Windows platform, users can select one of the printers configured in the system. In Linux platform, make sure ‘lpr’ command works.

5.3.3.4 Exit

Exit GofTrace window.

5.3.4 Schematic Menu

5.3.4.1 New Schematic

This command launches a new GofTrace schematic window.

5.3.4.2 List Gate

This command pops up a window for user to enter a string into the entry to find the matching instances. It accepts wildcards in both hierarchy name and instance name. For example, there are four hierarchical instances u_lane0, u_lane1, u_lane_2, u_lane3, each instance has spare modules with instance naming ‘u_spare*’, and in each spare module AND gate has instance naming ‘*AND*’. In order to find all the spare AND gates, one can enter a string ‘u_lane*/u_spare*/*AND*’.

5.3.4.3 Load Gate

This command pops up a window for user to enter a string into the entry to load the matching instances onto the schematic. Same as ‘List Gate’ command above, it accepts wildcards. However, the total number of gates drown on the schematic should not exceed the threshold defined in Menu Options->Setup->Misc->’Gates number limit’.

5.3.4.4 Load Gate Driving Net

This command pops up a window for user to enter a string into the entry as the net name. The tool will find the driver of the net and draw the driver on the schematic.

5.3.4.5 List Selected Instances

Use mouse-left-button to select a bunch of objects (Instances or wires) on the schematic. Click this command to list all the selected instances’ full hierarchical names in a pop window.

5.3.4.6 List Selected Wires

Use mouse-left-button to select a bunch of objects (Instances or wires) on the schematic. Click this command to list all the selected wires’ full hierarchical names in a pop window.

5.3.4.7 List Selected Modules

Use mouse-left-button to select a bunch of objects (Instances or wires) on the schematic. Click this command to list all the selected gates’ module name in a pop window.

5.3.4.8 List Selected Instances Definitions

Use mouse-left-button to select a bunch of objects (Instances or wires) on the schematic. Click this command to list all the selected instances’ full definitions in a pop window.

5.3.4.9 List Selected Gates Types

Use mouse-left-button to select a bunch of objects (Instances or wires) on the schematic. Click this command to list logic type numbers of all the selected gates in pop window. For example, ‘AND’ gate has type ‘and’, inverter has type ‘not’. The pop window can have information such as “Type ‘not’ has 11”.

5.3.4.10 Zoom In

This command can zoom in the schematic view. The maximum zoom in ratio is 100%. Keyboard shortcut for this command is key ‘+’.

5.3.4.11 Zoom Out

This command can zoom out the schematic view. The minimum zoom out ratio is 13%. Key board shortcut for this command is key ‘-‘.

5.3.4.12 Zoom to

This command can directly select zoom ratio, the valid values are 100%, 67%, 44%, 30%, 20% and 13%.

5.3.4.13 Find Gates on Schematic

This command pops up a window for users to enter a string to find the matching instances on the schematic. It matches portion of the full name. For example, ‘U’ matches ‘U0’, ‘U1’ and ‘U222’.

5.3.4.14 Find Nets on Schematic

This command pops up a window for users to enter a string to find the matching wires on the schematic. It matches portion of the full name. For example, ‘Net0’ matches ‘Net0’, ‘Net011’ and ‘Net023’.

5.3.4.15 Undo Schematic Operations

This command is to undo schematic operations. Keyboard shortcut is Ctrl-z.

5.3.4.16 Place & Route

This command group is to automatically place the gates on the schematic and automatically route the wires.

5.3.4.16.1 Auto Place & Route

This command is to do bother placement and routing automatically.

5.3.4.16.2 Auto Place

This command is to do automatic placement only.

5.3.4.16.3 Auto Route

This command is to do automatic routing only.

5.3.4.16.4 Reset Route

This command is to reset all existing routes, all routed wires become straight.

5.3.4.17 Create PS/PDF File

This command is to create Postscript file or PDF file for the current view of the schematic. In Windows platform, only Postscript is support. On Linux platform both Postscript and PDF are supported.

5.3.5 Commands Menu

5.3.5.1 View Gates in Layout

This command launches layout viewer window. If some gates and wires are selected on the schematic, they will be highlighted on the layout viewer. It requires DEF and LEF physical design files to be loaded.

5.3.5.2 Load Layout Files

This command is to load layout physical design files. They include DEF and LEF files. The command can be run several times to load the physical design file one by one. DEF and LEF files can be loaded by command line with -def and -lef options.

5.3.5.3 Launch GofCall Script Interface

This command launches GofCall Script Interface window.

5.3.5.4 Spare Cells

This command group handles spare cells in automatic metal ECO flow.

5.3.5.4.1 Create Spare Cells File

This command creates spare cells file. The spare cells are instances in the netlist file with special naming convention defined in Menu Options->Setup->GofECO->Setup->SpareCellPattern

5.3.5.4.2 Load Spare Cells File

This command loads the spare cells file created by the command above.

5.3.5.5 Launch Files Compare Window

This command launches netlist files compare window.

5.3.5.6 Process Timing Violations

This command launches Prime Time report file processing controller.

5.3.5.7 SDF

This command group handles SDF loading.

5.3.5.7.1 Create SDF Index File

This command creates SDF file index file. GOF doesn’t load the full SDF file, but SDF index file instead.

5.3.5.7.2 Load SDF Index File

This command loads SDF index file created by the command above.

5.3.6 Options Menu

5.3.6.1 Increase Font Size

This command increases the font size on the schematic.

5.3.6.2 Decrease Font Size

This command decreases the font size on the schematic.

5.3.6.3 Show Port

This option makes port name visible.

5.3.6.4 Show Wire

This option makes wire name visible.

5.3.6.5 Show Title

This option makes gate title visible.

5.3.6.6 Show Type

This option makes gate type visible.

5.3.6.7 Show Connections

This option makes wires visible.

5.3.6.8 Show Comment

This option makes comments visible.

5.3.6.9 Dump Waveform Restore File

This command pops up a window to setup simulation waveform restore file. Four waveform restore file formats are supported.

· SimVision Restore File

· ModelSim Restore File

· Verdi Restore File

· GtkWave Restore file

If one or more of the formats are selected, GofViewer and GofTrace pop menus will have ‘Write Selected Nets to the Waveform Restore File’ as the first item, when a net is selected.

5.3.6.10 Save String to Clipboard

This option enables saving string to clipboard when a wire or instance name is clicked by mouse-left-button.

5.3.6.11 Cursor Mode

This is normal mode of the schematic tracing.

5.3.6.12 Line Edit Mode

This mode sets cursor in editing wire connections mode. Press mouse-left-button on the straight wire connection and move, the line will be pulled by the cursor until the mouse button is released.

5.3.6.13 Setup

The command pops up configuration window for the tool setup.

5.3.7 Help Menu

5.3.7.1 General

General help information.

5.3.7.2 About

About Gates On the Fly.

5.3.7.3 nandigits.com/gof_manual.htm

Visit the website for the manual.

5.3.8 Keyboard Shortcuts

5.3.8.1 Access Menu

Press key ‘Alt’ and underlined letter in menu.

5.3.8.2 Functions access

· Ctrl-c: Copy the selected objects

· Ctrl-v: Paste the content in clipboard copied by Ctrl-c

· Ctrl-g: Load instance to schematic

· Ctrl-w: Write to waveform dump restore file

· Ctrl-x: Exit the current window

· Ctrl-digit: Save the selection location as the digit indication, the schematic view will move the current saved location when the digit is pressed later

5.3.9 Selection Status

Click mouse-left-button on the schematic window, the object which can be net, instance under the cursor is highlighted. GofTrace pop menu has different content according to the selection status. Pressing keys Ctrl-a can have all selected on the schematic. Press mouse-left-button and don’t release, move mouse down to select multiple objects.

5.3.10 GofTrace Pop Menu

Click mouse-right-button on GofTrace schematic, a menu pops up. The content of the menu varies as the selection status on the schematic.

5.3.10.1 Nets Equivalence Check

The command needs the reference netlist loaded.

· The reference netlist can be loaded by '-ref' option in command line. For example, "gof -lib tsmc.lib implementation.v -ref reference.v"

· The reference netlist can be loaded by 'read_design' with '-ref' switch in GofCall script. For example, 'read_design("-ref", "reference.v")'

Use mouse-left-button to select on a pin in implementation netlist and press 'ctrl' key to click mouse-left-button on the other pin in reference netlist. So that one pin in implementation netlist and the other comparing pin in reference netlist are selected at the same time.

Click mouse-right-button to popup menu and select 'Equivalence Check for 'neta' vs 'netb'" command.

Figure 32: Nets Equivalence Check

The example above selects normal hierarchical Equivalence Check mode, and the other Equivalence Check mode is flatten mode which differs the hierarchical mode in that it flattens the hierarchies to extract logic cone ending at sequential cells (FlipFlops) and top level input ports.

When the check is done, a pop window shows if the nets are equivalent. After the check is done, the tool keeps all equivalence information for every instance in the logic cone. Use mouse-middle-button to expand the schematic, the information is marked as 'GOF_enet###'. It's very convenient for Logic Equivalence Failure debug. For example, in Figure 12, 'u_mt_core.u_rtc3.Uinv0' was added in time ECO and it was caught by the tool by showing as inverted logic.

5.3.10.2 Find Logic Equivalent Nets

Wire names in RTL codes are normally optimized away in synthesis process. GOF has a way to retrieve them. A reference netlist with the wire names preserved should be synthesized. There are several ways to preserve wire names.

· Put the wires in output ports

· Use 'preserve' command in synthesis constraint file

The reference netlist should be loaded with the implementation netlist.

· The reference netlist can be loaded by '-ref' option in command line. For example, "gof -lib tsmc.lib implementation.v -ref reference.v"

· The reference netlist can be loaded by 'read_design' with '-ref' switch in GofCall script. For example, 'read_design("-ref", "reference.v")'

Start GUI Window, load the preserved wires on a schematic window. Select the pin that drives the wire, right click mouse-right-button to popup menu. Select 'List Logic Equivalent Nets of …' command.

Figure 33: List Logic Equivalent Nets

A popup window appears to list the nets that Logically Equal or Invert to the reference net. By popup menu on the window, the corresponding nets can be easily loaded into the schematic.

Figure 34: Logic Matching Nets

The feature is very convenient in manual ECO when the optimized wires have to be located in the implementation netlist.

5.3.10.3 Find Circuit between Two Points

When two or more than two instances are selected on the schematic, the command item appears in the pop menu. This command finds the combination logic path between two instances.

5.3.10.4 Add Comments

This command adds comments entered by users on the schematic.

5.3.10.5 Find Gates on Schematic

See Find Gates on Schematic.

5.3.10.6 Find Nets on Schematic

See Find Nets on Schematic.

5.3.10.7 Place & Route

See Place & Route.

5.3.10.8 Show Logic Cone

Logic Cone is the logic cluster between flops and ports, as shown in the following figure. Users should select the output flop or its pins to do logic cone extraction.

Figure 35: Logic Cone

5.3.10.8.1 On the Schematic

Draw the whole logic cone on the schematic.

5.3.10.8.2 In Text Mode

Draw the whole logic cone in a pop up text window.

5.3.10.9 Copy Selected to

This command group does interactions between GofTrace windows and LayoutViewer windows.

5.3.10.9.1 Schematic New

Copy the selected items to a new schematic.

5.3.10.9.2 Schematic Number#

Copy the selected items to an existing schematic identified by ID Number.

5.3.10.9.3 Layout New

Copy the selected items to a new launched LayoutViewer window. The selected circuit will be marked on the LayoutViewer window.

5.3.10.9.4 Layout Number#

Copy the selected items to an existing LayoutViewer window indentified by ID Number.

5.3.10.10 Find selected in GofViewer

This command finds the selected instance back in GofViewer netlist window, and highlights the instance in the netlist window.

5.3.10.11 Edit Gate Display

This command pops up a window for users to add or change comments associated with the gate and change the color of the gate.

5.3.10.12 List Logic for the Selected Leaf Cell

This command pops up a text window to list the logic of the selected leaf cell.

5.3.10.13 List Context for the Selected Leaf Cell

This command pops up a text window to list the library content of the selected leaf cell. The content includes the cell’s pin definitions, area and timing.

5.3.10.14 List Definition for the Selected Instance

This command pops up a text window to list the instantiation of the selected instance.

5.3.10.15 Load Instance Similar to the Selected Instance

This command pops up an entry window with the current selected instance name pasted in the entry. So that user can do simple change to load other similar naming style instance onto the schematic.

5.3.10.16 Equivalent Symbol

This command changes the selected gate symbol display to the equivalent symbol according to DeMorgan's Laws. For example, NAND symbol is equivalent to Inputs Inverted OR symbol.

5.3.10.17 Delete

This command deletes the selected objects on the schematic. The object can be gates, wires and comments.

5.4 GofECO

GofECO uses the same window as GofTrace by enable ECO mode. The background color changes to light blue by default. The color can be configured by Menu Setup->GofECO->Color->BackGround. The ECO operation icons appear on the tool bar. GofECO uses the same menus GofTrace uses, besides the contents in ECO menu being activated.

Figure 36: GofECO Window

5.4.1 ECO Menu

5.4.1.1 Enable ECO and ECO Preferences

This option enable ECO mode, GofTrace switches to GofECO. A pop up window appears for inputting ECO setups.

Figure 37: ECO Preferences

· ECO Name should be unique, so that name confliction can be avoided

· ECO Header Comment is optional, which will appear at the beginning of ECO netlist file

· ‘Metal only’ enables automatic metal ECO flow

· ‘Delete floating gates’ enables deletion of output floating gate when saving ECO result

5.4.1.2 Insert Gates

This command inserts gates in the selected wires. It requires one or more wires being selected on the schematic, before inserting gates. A ‘Gate selection’ window pops up for users to select proper type of gates and gate number. When multiple wires are selected and some wires have the same drivers, users can choose either one gate driving all shared wires or one gate driving each wire. Users will be asked to choose the pin connections in ‘Specify pin connections’ window. The default pin connections setup can be used and users can modify the connections later on the schematic. Read this PDF use case for more detail.

http://www.nandigits.com/use_cases/gof_insert_buffers_inverters.pdf

5.4.1.3 Replace Gates

This command replaces the selected gates with a different type of gates. It requires one or more gates being selected on the schematic. If two or more than two gates are selected, they should have the same type. A ‘Gate selection’ window pops up for users to select proper type of gates to replace the selected ones. Users will be asked to choose the pins connections in ‘Specify pin connections’ window. The default pin connections setup can be used and users can modify the connections later on the schematic.

5.4.1.4 Add Gates

This command adds new ECO gates on the schematic. A ‘Gate selection’ window pops up for users to select proper type of gate to add onto the schematic. The new ECO gates appear as output driving a new net and input floating. The hierarchy of the gate is undefined. When users connect one of the input pins to another existing gate or connect other gate’ floating input to the ECO gate’s output pin, the ECO gate gets the same hierarchy as the other gate. Read Add Connections for more detail.

5.4.1.5 Delete Selected Items

This command deletes the selected items. Users would be warned for deleting multiply objects at the same time.

5.4.1.6 Upsize Drive Strength

This command upsizes the selected gate to a higher drive strength gate with the same type. If there is no higher drive strength gate available, users would be warned with a pop up information window.

5.4.1.7 Downsize Drive Strength

This command downsizes the select gate to a lower drive strength gate with the same type. If there is no lower drive strength gate available, users would be warned with a pop up information window.

5.4.1.8 Undo ECO Operations

This command undoes the previous ECO operation, until no more ECO operation is in the pipeline.

5.4.1.9 Claim Spare Gates

This command is used in Automatic Metal ECO, ‘Metal only’ should be checked in ECO preferences configuration. It pops up a text window to list which spare gate can be mapped to for each ECO gate.

5.4.1.10 Save ECO

This command saves ECO result to a file. The supported file formats:

· Verilog netlist

· GofCall Perl Script

· SOC Encounter ECO script

· Tcl script for Synopsys

· DC script for Synopsys

5.4.2 Metal ECO

GUI mode automatic metal only ECO is for experimental purpose. GofCall script mode metal only ECO is recommended.

Metal ECO only touches metal layers. There are two ways to do metal ECO. Automatically mapping spare gates and manually handling spare gates.

5.4.2.1 Automatically Mapping Spare Gates

· Load spare cells list file, it can be loaded by command line with -sparelist option

· Load DEF/PDEF files, it can be loaded by command line with -def option

· Enable ‘Metal Only’ option in ECO Preferences

· ECO gates will be only available from the spare cells list

· When ECO is done, press button ‘Claim spare gates’

· Spare gates replacement status window shows the detail replacement

· When save ECO result to SOC Encounter ECO script, these new added ECO gates use the location of the corresponding spare gates

o DETACHTERM U87 A0 n54

o DELETEINST spare_CLKINVX1_119

o ADDINST -inst eco012345_ECOCELL_0 -cell CLKINVX1 -loc 2153.72 11.07

o ADDNET eco012345_wire0

o ATTACHTERM eco012345_ECOCELL_0 Y eco012345_wire0

o ATTACHTERM eco012345_ECOCELL_0 A n54

o ATTACHTERM U87 A0 eco012345_wire0

Figure 38: Claim spare gates

5.4.2.2 Manually Handling Spare Gates

This flow requires users to decide which spare gates to use in metal ECO. Users checks LayoutViewer to find out what is the closest right type spare gate. Read this PDF use case for more detail.

http://www.nandigits.com/use_cases/gof_metal_eco.pdf

5.5 LayoutViewer

LayoutViewer window displays partial physical placements. The circuit drawn on the schematic can be highlighted on LayoutViewer. It has full interactivity with GofTrace. It requires physical design files including DEF and LEF files to be loaded.

Figure 39: Layout View Window

5.5.1 File Menu

5.5.1.1 Capture in PDF

This command saves the current LayoutViewer display to PDF file. It is only supported in Linux Platform.

5.5.1.2 Exit

Exit LayoutViewer.

5.5.2 View Menu

5.5.2.1 Show Grid

This option shows grid on LayoutViewer.

5.5.2.2 Show Instance

This option shows instance name on LayoutViewer.

5.5.2.3 Show Module

This option shows module name on LayoutViewer.

5.5.3 Help Menu

5.5.3.1 nandigits.com/gof_manual.htm

Visit NanDigits web site for Gates On the Fly manual.

5.5.4 LayoutViewer Pop Menu

Click mouse-right-button to pop up the menu.

5.5.4.1 Clear Circuit Markers

This command clears circuit markers which were mapped from GofViewer.

5.5.4.2 Clear Searching Markers

This command clears searching markers which were activated by search function.

5.5.4.3 Copy Selected to

This command copies the selected gates to the following destination:

· Back to GofViewer

· A new Schematic

· An existing Schematic indentified by Number ID

6 Appendix A

6.1 GOF Command Options

gof [options] netlists

options:

-h: Print out this info.

netlists: Load netlist. There can be multiple netlist files listed,

if the design has more than one netlist files.

-lib technology_library: Or '-synlib technoloty_library', Load in technology library (synthesis library)

which has parameters for leaf gates.

There can be multiple -lib options,

if the design has more than one technology library files.

-v simulation_library: Specify simulation library file name which has Verilog definition

for leaf gates, like AND2X4.

There can be multiple -v options, if the design has more than one simulation library.

Both -v and -lib options are for leaf gates definition.

But -lib can support more features, like logic cone extraction.

In some cases, some leaf cells don't have technology library,

simulation lbrary is used instead to resolve the cells.

-v option can coexist with -lib option.

-vmacro macro_library_file: For ECO purpose. Each module in the file appears as leaf cell, and it can be

added like other leaf cell in ECO.

When write out ECO netlist, the file content appear in the beginning of ECO netlist. And the

ECO cell is added as a hierarchical sub-block.

-y library_directory: Specify library directory, one file corresponds to one leaf gate.

+libext+.v should be used with -y option.

+libext+.v: Specify library file extension in library directory.

it can be +libext+.v+.vg+.vlib,

if .vg and .vlib are also lib extensions.

-run script_file.pl: Invoke GofCall to run netlist processing script, GOF will stay in shell mode when the

script finishs.

-vn library_name: Specify none leaf gates library file. For example, a file has

collection of macro cell which is defined by leaf gates.

-yn library_directory: The files in the directory are not defining leaf gates.

-shell: Run in text mode with shell prompt, GofCall APIs can be run in interactive mode in shell

-o log_file: Save log file, default gatesof.log

-Top_1 netlist_files: Load another netlist files to build Top_1 tree. The hierarchy will shown up in left

side of GofViewer window.

You can use -Top_2 -Top_3 ... to load more netlist files.

Note, when this option takes all netlist files followed, so the main netlist files should appear

before this option

For example, 'gof -lib tsmc.lib revised_netlist1 revised_netlist2 -Top_1 golden_netlist1

golden_netlist2' will create two trees in the left side of GofViewer window.

While, ‘gof -lib tsmc.lib -Top_1 golden_netlist1 golden_netlist2 revised_netlist1

revised_netlist2' will build only one tree, since Top_1 option eats up all of the netlist files, the main tree is gone.

+define+PARAMETER0+PARAMETER1: Define PARAMETER0 PARAMETER1.

-id mydesign: Specify design id will appear on tile. Optional.

-def def_file: Load DEF, design exchange format, file.

-lef lef_file: Load Library Exchange Format file

-pdef pdef_file: Load in pdef file.

There can be multiple -pdef options,

if the design has more than one pdef files.

DEF file is preferred if both DEF and PDEF files are available.

-gtech gtech_file: Load in gtech file for wire matching.

-sparelist spare_cells_list_file: Load in spare cells list file.

-f file_list_file: Load all the files and options in the file_list_file

-vcd vcd_file: Load in VCD file for schematic annotation

-textbutton: Text mode button instead of image mode button in ECO operations

-version: Print out current version

-licquery: Query license usage

6.2 Command line Examples

gof -lib tsmc.lib soc.v

--- You have one netlist file 'soc.v' and one technology library, 'tsmc.lib'

gof -lib tsmc_std.lib -lib tsmc_io.lib top.v part0.v part1.v

--- You have three netlists, top.v, part0.v and part1.v, two technology library files

standard library cell, tsmc_std.lib, IO cells, tsmc_io.lib

gof -lib tsmc_std.lib -lib tsmc_io.lib -v analog_models.v top.v part0.v part1.v

--- Some analog cells having no technology library,

using '-v' option instead to load in analog simulation library

gof -lib tsmc_std.lib -lib tsmc_io.lib -vn macros.v -v analog_models.v top.v part0.v part1.v

--- macros.v has defined macro cells like sync-cells

gof -v /home/lib/tsmc_cells.v /home/netlist/soc.v

--- You would rather to use simulation library instead of technology library

gof -v /home/lib/tsmc_cells.v -v /home/lib/macro_cells.v +libext+.v -y /home/lib /home/netlist/top.v

/home/netlist/soc.v

--- Multiple simulation library files, and some leaf cells are defined in '/home/lib' directory,

which uses '-y' option to resolve them

gof -v /home/lib/tsmc_cells.v +libext+.v -y /home/lib -yn /home/vmodule /home/netlist/soc.v

--- '/home/vmodule' has some macro cells files

gof -v /home/lib/tsmc_cells.v /home/netlist/soc0.v /home/netlist/soc1.v -id the_soc_design

--- You would like to display 'the_soc_design' as the title

gof -lib tsmc.lib -def soc.def.gz -lef libcell.lef soc.v

--- Design Exchange Format file soc.def.gz. And library exchange format file. For layout view usage

gof -v /home/lib/tsmc_cells.v /home/netlist/soc.v -gtech soc_submod.gtech.gv

--- Load in gtech file for RTL wire to netlist mapping

gof -lib tsmc.lib soc.v -run scripts.pl

--- Process netlist with scripts.pl in text mode, scripts.pl is in perl syntax

gof -lib tsmc.lib revised_netlist.v -Top_1 golden_netlist.v

--- Load both revised netlist and golden netlist, it's good for netlist comparison

7 Appendix B

7.1 Fatal codes:

F-000: License check out failure

F-001: Time out in adding ports in hierarchies

F-002: Empty ID for nets

F-003: Pin connections processing fatal error

F-004: Net id not defined

F-005: Net is not in End point hash

F-006: Instance has not been mapped position in AUTO ECO

F-007: Instance has no name mapping in AUTO ECO

F-008: No net found for ECO instance/pin

F-009: Unknown connection type of instance/pin in AUTO ECO

F-010: Net has no name mapping in AUTO ECO

F-011: Failed to initialize database

F-012: Mcell get sub-chains error

F-013: No tree has been defined

F-014: No ID for leaf cell pin

F-015: Undefined subroutine in GofCall script

F-016: Global symbol requires explicit package name

F-017: Syntax Error

F-018: Illegal Division by zero

F-019: Bare word not allowed

F-020: Can't locate Perl module

7.2 Error codes:

E-001: Reference netlist has not been loaded

E-002: DEF file has missing section

E-003: Command line needs an option for a switch

E-004: Liberty files have not been loaded

E-005: Library cell doesn't exist

E-006: Delete middle bit in a bus

E-007: Unknown command line option

E-008: Win32 doesn't support .gz file

E-009: DEF file doesn't have DIEAREA item

E-010: Files loading sequence

E-011: Instance or pin or port can't be found in module

E-012: Net doesn't exists in module

E-013: Tree name doesn't exist

E-014: Hierarchical module name doesn't exist

E-015: Miss argument

E-016: Module stack is empty, too many pop_top

E-017: 'instance/pin' has wrong format

E-018: Instance or module doesn't exist

E-019: Instance doesn't have pin

E-020: Item is a black box

E-021: Missing DEF file

E-022: No reference for instance

E-023: 'leaf/pin' doesn't exist

E-024: Power connection format is wrong

E-025: Spare cell pattern is not specified

E-026: Spare list file doesn't exist

E-027: 'get_spare_cells' run before 'map_spare_cells'

E-028: 'instance/pin' is floating

E-029: New instance conflicts with existing one

E-030: Specify leaf:num in more than one output leaf

E-031: Instance should be leaf in change_gate

E-032: Syntax error in pin mapping

E-033: The new gate type should be different from the old one in change_gate

E-034: Leaf cell doesn't exist in libraries

E-035: Net doesn't have a driver

E-036: Instance name has special character that the tool doesn't support

E-037: Wrong argument in ECO APIs

E-038: Net has multiple drivers

E-039: Not a port

E-040: New port conflicts with existing one

E-041: Single bit wire can't be expanded to a bus

E-042: New port direction conflicts with existing one

E-043: Commands loading sequence

E-044: Nets in one ECO command should be in the same hierarchy

E-045: Missing scan control pins

E-046: Reference netlist is not loaded

E-047: Fail to open file for write

E-048: Fail to open file for read

E-049: Unable to recognize file format

E-050: Command line option needs a value

E-051: Path doesn't exist

E-052: Leaf should have only one output pin

E-053: New net conflicts with existing one

E-054: Instance ECO result not consistent

E-056: Net has no driver

E-057: Net has invalid BDD

E-059: Not enough resource to run synthesis

E-060: Not valid patch file

E-061: No spare cell for one gate type

E-062: Output port is driven by input port

E-063: Reference register doesn't exist in implementation netlist

E-064: No inverter in the database

E-067: Should add instance into fix_logic argument

E-071: Port doesn't exist in hierarchical instance

E-072: Black box instance doesn't exist in implementation netlist in AUTO ECO

E-076: Spare cells list file has Wrong format

E-080: GOF_KEY_FILE variable has not been defined

E-081: Use '-run' to run Perl script

E-082: Gtech file doesn't exist

E-085: Syntax error in netlist

E-101: No hierarchical path is used

E-102: Interrupt GUI operation by user

E-103: 'read_def' should be run before 'get_spare_cells'

E-105: Load specific file without the right option

E-106: Source ID can't be deleted

E-109: Found combinational loop

7.3 Warning codes:

W-001: Bypass already loaded file

W-002: DEF has some section missing

W-003: DEF has module not resolved

W-004: No ECO pin specified for ECO instance

W-005: Not enough spare cells

W-006: DEF file not loaded

W-007: Leaf cell doesn't have timing table

W-023: 'leaf/pin' doesn't exist

W-028: 'instance/pin' is floating

W-038: Net has multiple drivers

W-054: Instance ECO result not consistent

W-055: Net ECO result not consistent

W-056: Net is not driven

W-060: Invalid patch file

W-061: No spare cell for one gate type

W-065: Tie floating input pin to zero

W-066: New port created in AUTO ECO

W-068: Hierarchical cell is created in AUTO ECO

W-069: Set don't touch Warning

W-070: Can't find repeaters

W-073: 'instance/pin' is inverted but being forced to be equal by user

W-074: 'instance/pin' is forced to be inverted by user

W-075: Net returned wrong BDD

W-077: No size information for a leaf

W-078: Module is redefined

W-079: Instance can't be resolved in GTECH

W-080: Leaf cell can't be resolved in module

W-083: Can't read MAC Address

W-084: Sub-module can't be resolved

W-086: Include file doesn't exist

W-087: Bit-width mismatch in instantiation

W-088: Zero fanin endpoint

W-089: Can't find ECO instance position

W-090: Empty instance name in patch file

W-091: ECO net has no fanout

W-092: New input port created and needs to be connected

W-093: New ID created for end point

W-094: Can't detect port phase in module

W-095: Port or net is forced to be equal by user

W-096: Port and net has mismatching bit-width

W-097: Schematic only feature

W-098: Force to use 1'b0/1'b1 in AUTO ECO

W-099: Can't fix timing, since lacking valid points

W-100: No lib name for a leaf cell

W-104: Module is defined as leaf cell but has definition in the netlist