NanDigits Design Automation

Usage: gof [options] netlists
GOF options:
  -h:               print out this info.
  -lib technology_library: Or '-synlib technoloty_library', Load in technology library (synthesis library) 
                    which has parameters for leaf gates. 
                    There can be multiple -lib options,
                    if the design has more than one technology library files.
  -v simulation_library:  Specify simulation library file name which has verilog definition 
                    for leaf gates, like AND2X4.
                    There can be multiple -v options, if the design has more than one simulation library.
                    Both -v and -lib options are for leaf gates definition.
                    But -lib can support more features, like logic cone extraction.
                    In some cases, some leaf cells don't have technology library, 
                    simulation lbrary is used instead to resolve the cells. 
                    -v option can coexist with -lib option.
  -y library_directory: Specify library directory, one file corresponds to one leaf gate.
                    +libext+.v should be used with -y option.
  +libext+.v:       Specify library file extension in library directory.
                    it can be +libext+.v+.vg+.vlib, 
                    if .vg and .vlib are also lib extensions.
  -run script_file.pl:  Invoke GofCall to run netlist processing script, Gof will stay in shell mode when the script finishs.
  -vn library_name: Specify none leaf gates library file. For example, a file has 
                    collection of macro cell which is defined by leaf gates. 
  -yn library_directory: The files in the directory are not defining leaf gates. 
  -shell:           Run in text mode with shell prompt, GofCall APIs can be run in interactive mode in shell
  -o log_file:      Save log file, default gatesof.log
  netlists:         Load netlist. There can be multiple netlist files listed, 
                    if the design has more than one netlist files.
  -Top_1 netlist_file: Load another netlist file to build Top_1 tree. The hierarchy will shown up in left side of GofViewer window.
                       You can use -Top_2 -Top_3 ... to load more netlist files.
  +define+PARAMETER0+PARAMETER1:    Define PARAMETER0 PARAMETER1.
  -id mydesign:  Specify design id will appear on tile. Optional.
  -def def_file:    Load DEF, design exchange format, file. 
  -lef lef_file:    Load Library Exchange Format file
  -pdef pdef_file:  This option is slowly phasing out. Use -def instead
                    Load in pdef file.  
                    There can be multiple -pdef options, 
                    if the design has more than one pdef files.
  -gtech gtech_file: Load in gtech file for wire matching.
  -sparelist spare_cells_list_file: Load in spare cells list file.
  -f file_list_file: Load all the files and options in the file_list_file
  -vcd vcd_file:    Load in VCD file for schematic annotation
  -textbutton:      Text mode button instead of image mode button in ECO operations
  -version:         Print out current version
  -licquery:        Query license usage
-------------------------------------------Examples-----------------------------------------
  gof -lib tsmc.lib soc.v
      --- You have one netlist file 'soc.v' and one technology library, 'tsmc.lib'
  gof -lib tsmc_std.lib -lib tsmc_io.lib top.v part0.v part1.v
      ---  You have three netlists, top.v, part0.v and part1.v, two technology library files
           standard library cell, tsmc_std.lib, IO cells, tsmc_io.lib
  gof -lib tsmc_std.lib -lib tsmc_io.lib -v analog_models.v top.v part0.v part1.v
      ---  Some analog cells having no technology library, 
           using '-v' option instead to load in analog simulation library
  gof -lib tsmc_std.lib -lib tsmc_io.lib -vn macros.v -v analog_models.v top.v part0.v part1.v
      ---  macros.v has defined macro cells like sync-cells
  gof -v /home/lib/tsmc_cells.v /home/netlist/soc.v
      ---  You would rather to use simulation library instead of technology library
  gof -v /home/lib/tsmc_cells.v -v /home/lib/macro_cells.v +libext+.v -y /home/lib /home/netlist/top.v /home/netlist/soc.v
      ---  Multiple simulation library files, and some leaf cells are defined in '/home/lib' directory, 
           which uses '-y' option to resolve them
  gof -v /home/lib/tsmc_cells.v +libext+.v -y /home/lib -yn /home/vmodule /home/netlist/soc.v
      ---  '/home/vmodule' has some macro cells files
  gof -v /home/lib/tsmc_cells.v /home/netlist/soc0.v /home/netlist/soc1.v -id the_soc_design
      ---  You would like to display 'the_soc_design' as the title
  gof -lib tsmc.lib -def soc.def.gz -lef libcell.lef soc.v
      ---  Design Exchange Format file soc.def.gz. And library exchange format file. For layout view usage
  gof -v /home/lib/tsmc_cells.v /home/netlist/soc.v -gtech soc_submod.gtech.gv
      ---  Load in gtech file for RTL wire to netlist mapping
  gof -lib tsmc.lib soc.v -run scripts.pl
      ---  Process netlist with scripts.pl in text mode, scripts.pl is in perl syntax
  gof -v simulation_lib.v top.v netlist.vg -vcd top.vcd
      ---  Load in VCD file for schematic annotation
  gof -lib tsmc.lib revised_netlist.v -Top_1 golden_netlist.v
      ---  Load both revised netlist and golden netlist, it's good for netlist comparison