USE CASES

Automatic ECO cases

• Automatic Functional ECO
• RTL to RTL Supplemental ECO Flow
• RTL Patch ECO
• Automatic Functional ECO, Partial Mode
• Automatic Standard Cell Metal Only ECO
• Spare Gates Mapping in Metal Only ECO
• Constraint on Spare Gates Type and Number
• Metal Configurable Gate Array Spare Cells ECO
• DFT Constraints for Automatic Functional ECO and LEC
• Flip-flop Phase Inverted
• No Exact Pin Match
• Mixed Automatic and Manual ECO
• Clock Gating or MUX
• Reduce ECO Fix Scope
• Lockup Latches Handling in Automatic ECO
• Automatic Datapath ECO
• Convert Spare Gate Types

Script Mode Manually ECO cases

• TMR ECO in functional safety
• Swap instances to improve routing quality and timing
• Script Mode Manually Metal Only ECO
• Script Mode Modify State Machine and Debug
• Insert Isolation Gates in Low Power Design

GUI Mode Functional ECO cases

• GUI Mode Netlist Debug
• GUI Mode ECO Dynamic Demo
• Modify 3 bits state machine in GUI ECO
• Add reverse edge Flip-Flops
• Insert inverters (PDF)
• Add a hierarchical module (PDF)

GUI Mode Metal Only ECO cases

• GUI mode metal only ECO, one 'AND' spare gate is added

Gate Level Simulation Flow

• Gate level simulation (GLS) flow
• Remove 'x' in gate level simulation
• 'X' source tracing
• Gate level boundary optimization debug

Netlist Debug/Report

• Find equal nets in Implementation Netlist For Reference RTL wire
• Net names collision in Verilog to Spice conversion
• Clock tree fast trace
• Debug non-equivalent points after ECO
• Design Statistic
• Graphic mode vs Text mode
• Calculate clock gating percentage
• Debug Connectivity (PDF)
• Flexible Schematic generator
• Script Mode Modify State Machine and Debug
• Layout Placement Regions View
• Circuit Placement View on Layout