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set_top
Set the current top level module Usage: set_top($module); $module: Set $module as the current top level module, if the argument is missing, return the current setting
set_inverter
Set inverter, the tool will automatically pick one if the command is not called
Usage: set_inverter($inverter);
$inverter: Lib cell name for inverter
Example: set_inverter("INVX2");
push_top
Set the current top level module and push the previous setting to stack, pop_top can retrive it Usage: push_top($module); $module: Set the $module as the top level module, push the previous settting to the stack
pop_top
Pop out the saved top level module from the stack and discard current top level module setting Usage: pop_top;
get_conns
Get connections of net or pin in the top level module, return the leafs and the hierarchical connections
Usage: @result = get_conns($net_or_pin);
$net_or_pin: The net name or pin name that needs to get connections.
@result: a two dimension array
instance, port_name, pin_or_port, load_or_driver, is_it_a_leaf,
@result = ([instance_0, pin_0, 'pin', 'load', 1],
...
)
Example:
GOF > get_conns("n599");
Executing get_conns("n599");
gte_344 A[14] pin load 0
U198 Y pin driver 1
U94 AN pin load 1
# n599 has three connections, U198 is the driver
GOF > get_conns qcifhbeat
Executing get_conns("qcifhbeat");
qcifhbeat port load
U80 A pin load 1
qcifhbeat_reg Q pin driver 1
# qcifhbeat has three connections, it is output port of the current top level module
GOF > get_conns U187/A
Executing get_conns("U187/A");
U294 A1 pin load 1
U187 A pin load 1
U80 Y pin driver 1
get_drivers
Get the drivers of the net or pin
Usage: @drivers = get_drivers($point);
$point: net name or pin name, 'n12345' or 'U12345/A1'
@drivers: An array of the drivers, if the point is floating, @drivers is empty,
if the point has mulit-drivers, @drivers has more than one items.
For each item in @drivers
Index 0: instance, it will be empty if the driver is port
Index 1: pin or port, if the driver is port, return port
Index 2: string "pin" or "port" depending on the driver is port or leaf cell
E.G. @drivers = get_drivers("net12345");
@drivers has content of (["U1247", "Y", "pin"]);
@drivers = get_drivers("port_abc"); # port_abc is input port
@drivers has content of (["", "port_abc", "port"]);
get_net_of
Get the net name connecting to the pin Usage: my $net = get_net_of($pin); $pin: The pin of the instance, 'U1234.A1' or 'U1234/A1' $net: The net name connecting to the pin
get_cell_info
Get information of a module or instance
Usage: $data = get_cell_info($module_or_inst, @options);
$module_or_inst: The module or instance's name
@options:
-help: Print out this information
-conns: Get Connections of the item, only when it's instance
-type: Get the item's type information. It can be 'ff','latch','buf',
run 'get_lib_cells -type_info' for all existing type in the current libraries
-area: Get the area of the item
-leakage: Get the leakage of the item
-ref: Same as 'get_ref instance' if the item property is instance
$data: Returned data
In option is '-conns' case,
It is a hash having the following data structure
my $module = $hash->{module};
my $instance: $hash->{instance};
foreach my $port (keys %{$hash->{connections}}){
my $net = $hash->{connections}{$port};
}
If no option is present, it return the item's property
leaf_instance leaf_module hierachical_instance hierarchical_module
get_cells
Get all cells in the current module or and sub-modules
Usage: my @cells = get_cells($pattern, @options);
$pattern: The pattern matching instance name, '*', 'U*', 'U123' or '/UI_.*_./'
@options:
-help: Print out this information
-hier: Or -h, do the command hierarchically
-ref ref_pattern: Get cells that has reference matching ref_pattern, E.G. -ref OAI*
-type type_pattern: Type_pattern can be 'ff','latch','cg','not' ...
run 'get_lib_cells -type_info' for all existing type in the current libraries
-verbose: To print out reference with instance
@cells: Returned array with all instances matched
Examples,
get_cells('*') : Get all instances in the current module
get_cells() : Same as above
get_cells('U234*') : Get all instances matcing U234* in the current module
get_cells('/U../'); : Get all instances starting with U and followed by two characters, like U10, U99
get_cells('*reg_*_', '-hier') : Get all instances matching *reg_*_ hierarchically
get_cells('*', '-hier', '-ref', 'DFF*'); : Get all instances hierarchically and having reference matching DFF*
get_coord
Get cell's coordination
Usage: my ($x, $y) = get_coord($instance);
$instance: Instance name
Examples:
my ($x, $y) = get_coord("xbar/U1234");
# $x=100, $y=200 in um
get_nets
Get nets that matching pattern
Usage: @nets = get_nets($pattern);
$pattern: naming pattern.
@nets: returned net array.
Examples:
@nets = get_nets("*"); # get all nets.
@nets = get_nets("dbuffer_*"); # all nets with dbuffer as prefix
get_def
Get instantiation of instance, E.G. get_def('U78') to have AND2X1 U78(.A(n1), .B(n2), .Z(n3));
Usage: my $line = get_def($inst);
$inst: Instance name.
$line: The instantiating line
is_seq
Check if a leaf module is a specific sequencial cell
Usage: my $isseq = is_seq($name, @options);
$name: The leaf module under check
@options:
-help: This information
-ff: Check if it's flipflop
-latch: Check if it's latch
-cg: Check if it's gated clock
$isseq: 0, it is not the specific sequencial cell
1, it is the specific sequencial cell
is_leaf
Check if a module or instance is leaf cell
Usage: my $leaf = is_leaf($name);
$name: The module or instance under check
$leaf: 0, it's a hierarchical module, (Or the module is not defined)
1, it's leaf cell. Like, NAND4X8
get_modules
Get all hierarchical modules in the top level module
Usage: @modules = get_modules($pattern);
$pattern: Match pattern, can have wildcard "*", if it is empty, it will be treated as "*"
@modules: Array ("module0", "module1", ...)
Examples:
@modules = get_modules("*TM*"); # Any hierarchical modules with TM in the name.
@modules = get_modules; # All hierarchical modules.
get_instances
Get all hierarchical instances in the top level module
Usage: my @instances = get_instances($pattern);
$pattern: Match pattern, can have wildcard "*", if it is empty, it will be treated as "*"
@instances: Array of the hierarchical instances
Examples:
@instances = get_instances("UI_*"); # Any hierarchical instances with UI_ as prefix.
@instances = get_instances; # All hierarchical instances.
get_roots
Get root designs name Usage: my @rootdesigns = get_roots; @rootdesign: returned root designs name
get_ref
Get the reference of the instance, return leaf cell name or hierarchical module name Usage: $reference = get_ref($instance); $instance: Instance name, "U123" $reference: Return reference name, "NAND2X4"
get_ports
Get all ports matching the direction in the top level module
Usage: @matching_ports = get_ports($direction, $pattern);
$direction: Port direction, "input", "output", "inout" or "*". If it is empty, it will be treated as "*"
$pattern: Match pattern, can have wildcard "*". If it is empty, it will be treated as "*"
@matching_ports: Return ports matching the direciton in sub_module
Examples:
@ports = get_ports("input", "dsp2mc_*"); # Get input ports with "dsp2mc_" as prefix
@ports = get_ports; # Get all ports
get_pins
Get pins of instance or module
Usage: @pins = get_pins($instance, @options);
$instance: The instance name
@options:
-input: Get input pins
-output: Get output pins
-inout: Get inout pins
If no option is present, get all pins
@pins: All pins returned, in 'instance/pin' format
Example:
my @pins = get_pins("-input", "u_abc/U123");
return @pins has ("u_abc/U123/A", "u_abc/U123/B")
get_logic_cone
Get logic cone of nets or pins
Usage: $result = get_logic_cone($net_or_pin_list, @options);
@options:
-array: Return array of instances instead of a string
$net_or_pin_list: Nets or Pins list, should be in format of "U1/A,abc_reg/D,cde_reg/D"
$result: Returned string in verilog module format
Examples:
my $logic_cone = get_logic_cone("abc_reg/D,de_reg/D");
get_resolved
Resolve the relative path to module and leaf item
Usage: ($module, $leaf) = get_resolved($relative_path);
$relative_path: Relative path, like "u_abc/u_def/U456"
$module: Resolved module name, like "def"
$leaf: Resolved leaf name, like U456
Examples:
my ($module, $leaf) = get_resolved("u_abc/u_def/U456");
$module has value "def"
$leaf has value "U456"
gprint
Print out the message and save to log file Usage: gprint($info); $info: message to be printed.
exist_inst
Check if exist the instance my $ret = exist_inst($inst); $inst: The instance for checking $ret: 1: exists 0: not exist
exist_wire
Check if exist the wire my $ret = exist_wire($wire); $wire: The wire name for checking $ret: 1: exists 0: not exist
check_design
Check if the design has unresolved modules or other errors, like floating, multidrivers Usage: check_design;
get_lib_cells
Get leaf gates in libraries
Usage: my @cells = get_lib_cells($pattern, @options);
@options:
-help: This information
-char: All cells characterization
-type leaf_type: Get leaf gates matching type.
Leaf_type can be 'ff', 'latch', 'cg', 'buf', 'not', 'and' ...
-type_info: List all types in the current loaded libraries
-verbose: If $pattern match only one lib cell, the cell lib information will print out
$pattern: Library cell name pattern, can have '*'.
@cells: Return array with name matching
get_leafs_count
Get all leaf cells name and count in the top level module, return an array
Usage: @leaf_count = get_leafs_count;
@leaf_count: Arrary of leaf name and count
( [leaf0, cnt0], [leaf1, cnt1], ...)
Examples:
@leaf_count = get_leafs_count;
foreach my $leaf_point (@leaf_count){
my $leaf_name = $leaf_point->[0];
my $count = $leaf_point->[1];
print "LEAF: $leaf_name has $count cells\n";
}
get_leaf_pin_dir
Get leaf cell pin's direction input/output/inout Usage: my $dir = get_leaf_pin_dir($pin, $leaf_name); $pin: pin name, E.G. A or B or Y $leaf: Leaf cell name, E.G. NAND2X2 $dir: return direction, input/output/inout
strict_syntax
Use strict syntax, has same effect as 'use strict;' in perl script. Usage: strict_syntax;
set_quiet
Run script in quiet mode Usage: set_quiet;
set_verbose
Run script in verbose mode Usage: set_verbose;
set_max_lines
Set max output lines Usage: set_max_lines($num); $num: New max lines number. Default to be 500
set_keep_format
Set keep format of the original verilog when ECO is done Usage: set_keep_format($value); $value: 0: disable, 1 : enable.
set_power
Set power pins connections for leaf cell Usage: set_power($leaf_cell, $connections); $leaf_cell: Leaf cell name. Like NAND2X4 $connections: Power pins connections, like ".GND(GND),.VDD(VDD)"
gexit
Exit the GofCall interactive mode
Usage: gexit;
setup_eco
ECO command. Setup ECO
Usage: setup_eco($eco_name, $library_name);
$eco_name: ECO name, like eco01234
$library_name: When simulation library instead of technology library, that is
-v option is used instead of -synlib option in loading the design.
User has to specify library_name in this case which is for tcl format
ECO result writting out. If not specified, 'synlib' will be used as library name.
change_pin
ECO command. Modify pin connection in ECO.
Usage: Accept two types of argument, GOF automatically detects the type by check the reference of the second argument
1. Connect to net
change_pin($pin_name, $net);
$pin_name: In the format of "instance/pin", can be more than one pins separated by ",",
"instance1/pinA,instance2/pinB", E.G. "U123/A", "U123/A,U345/B"
Hierarchical naming style is supported as well, "u_abc/U123/A"
The pins have to be input in this mode.
$net: The net name the pin will connect to.
Hierarchical naming style is supported, "u_abc/net123"
When the pin and the net are in different hierarchies, ports will be added automatically
E.G. change_pin("u_abc/u_cde/U200/A", "u_xyz/u_stv/net300"); The tool will create 4 ports across the hierarchies
to connect the net to the pin.
change_pin("u_abc/u_cde/U200/A", "u_xyz/u_stv/U300/Y"); The tool will get the net tie to Y pin of U300 and
do the the same as the previous example.
2. Insert a new leaf cell to drive the pin
change_pin($pin_name, $leaf_cell, $new_instance, $connection);
$pin_name: In the format of "instance/pin", E.G. U123/A Hierarchical naming is supported, u_abc/U123/A
The pin can be output in this mode. The tool will get the net the pin drives,
and change the command to
change_net($thenet, $leaf_cell, $new_instance, $connection);
$leaf_cell: The leaf cell name to drive the $pin_name
$new_instance: The instance name for the new inserted leaf cell, optional, the tool will assign one if it's empty
$connection: The pins connection for the new cell.
Supported formats, 1. Detail format: ".A(net0),.B(net1),.C(net2)"
2. Simple format: Connect to the pins in alphabical sequence "net1,net0,net2"
3. Mixed format: "u_abc/U123/Y,.B(net1),net2"
3. Special format: "-" in the pin connections, to connect up the original net.
4. Advanced nesting format: change_pin("U189/A", "AOI21X2", "", "U190/Y,,BUFX6(BUFX6(BUFX6(n412)))");
Note: All strings should be quoted by ' or " to avoid syntax error or undisired effects.
If net or instance name has '\', single quotation has to be used.
The best choice is to omit the '\' in the name, the tool can automatically decide if '\' is needed in the name.
Examples: U123 has input pins A,B,C, U234 has input pins A0,A1,B
change_pin("U123/A", "net12345"); # Change A pin of U123 to net12345
change_pin("U123/B", $net); # Change A pin of U123 to $net which is defined in the ECO script.
change_pin("U123/A,U234/B", "net12345"); # Change A pin of U123 to net12345
change_pin("U123/A", "NAND2X2", "eco12345_U0", "net1234,net5678"); # Insert "NAND2X2 eco12345_U0(.A(net1234),.B(net5678));"
# to drive U123/A
change_pin("U123/A", "NAND2X2", "eco12345_U0", ".A(net1234),.B(net5678)"); # Same as above, with more detail of pin connections
change_pin("U123/A", "BUFFX4", "", "-"); #Insert a buffer to U123 A pin
change_pin("abc_reg_1_/CK", "NAND2X1", "", ".A(-),.B(1'b1)"); #Insert NAND2X1 to drive CK pin and new A connects to the original net
change_pin("u_abc/u_cde/U200/A", "u_xyz/u_stv/U300/Y"); # Do hierarchical connection
change_pin("qcif/num2/u_spare1/B", "AOI21X2", "eco_inst_on_top1", "NAND2X2(gte_344/u_smod/U100/Y, gte_344/n114), gte_343/U111, BUFX6(BUFX6(n105))");
change_gate
ECO command. Modify an instance in ECO, change the instance's type or pin connections depending on the argument contexts.
Usage: change_gate($instance, $new_reference, $pin_mapping);
change_gate($instance, $pin_connections);
$instance: The instance under ECO. Support hierarchical name, "u_abc/U123"
$new_reference: The new reference which the instance will change to, E.G. 'AND3X1'. If no reference is present,
the ECO operation is assumed to change the instance's pin connections.
$pin_mapping: Input pins mapping, ".new(old)", E.G. ".A1(A),.B1(B)"
if two references have same input pins. The option can be empty
$pin_connections: New pin connections, ".A(n242)", the unspecified pins will keep the original connection.
Examples:
U123 has reference OR3X1 with input pins, A,B,C originally
change_gate('U123', 'AND3X1', ""); #change U123 to AND3X1, all input pins are the same.
change_gate('U123', 'AND2X1', ""); #A and B keep the connections, discard C
change_gate('U123', 'AND2X1', ".B(C)"); #A keeps the connections, B connects to what the old C connects. And discard old B
change_gate('U123', 'AND4X1', ".D(n123)"); # A,B,C keep the same, and new D pin connects to net n123
change_gate('U123', 'AO21X1', ".A0(A),.A1(B),.B0(C)"); #AO21X1 has input pins, A0, A1 and B0
change_gate("U123", ".A(n123),.B(n124)"); # change U123 A to n123, B to n124, keep C connection.
change_gate("U123", ".A(B),.B(C),.C(A)"); # Rotating A/B/C connections.
change_net
ECO command. Change a exsiting net's driver
Usage: change_net($net, $gate, $instance, $connections);
$net: The net to be ECOed
$gate: New leaf gate to drive the net
$instance: The instance name of the new gate. Optional, if it is empty, assigned by the tool
$connections: The new gate input pins connections. If it is empty, the gate will be inserted in the connection
Supported formats, 1. Very detail ".A(net0),.B(net1),.C(net2)"
2. Connect to the pins in alphabical sequence "net1,net0,net2" indicating A->net1,B->net0,C->net2
3. Other instance/pin "U408/Y,U409/Y,net2" indicating A->U408/Y,B->U409/Y,C->net2
Example:
change_net("n123", "BUFX2", "", "n40"); # Drive n123 with BUFX2 driven by n40
change_net("n123", "AND2X2", "", "-,n40"); # Drive n123 with AND2X2 driven by n40 and original n123 driver
change_net("n123", "BUFX2"); # Insert a buffer into n123
change_port
ECO command. Change an output port's driver, or add gate after input port
Usage: change_port($port, $gate, $instance, $connections);
$port: The port to be ECOed, can be input port or output port
$gate: New leaf gate to drive the port if the port is output
Or add the gate after input port
$instance: The instance name for the new leaf cell, optional, the tool will assign one if it's empty
$connections: The new gate input pins connections. If it is empty, the gate will be inserted in the connection
Supported formats, 1. Very detail ".A(net0),.B(net1),.C(net2)"
2. Connect to the pins in alphabical sequence "net1,net0,net2" indicating A->net1,B->net0,C->net2
3. Other instance/pin "U408/Y,U409/Y,net2" indicating A->U408/Y,B->U409/Y,C->net2
new_net
ECO command. Create a new net
Usage: @return = new_net($new_net, $reference, $new_instance, $connections);
$new_net: The new net to be created, if not defined, the tool will assign one automatically
$reference: The leaf gate name to drive the net.
$new_instance: The instance name the new cell will have. Automatically assigned a name if left empty.
$connections: The new gate input pins connections
Supported formats, 1. Detail format: ".A(net0),.B(net1),.C(net2)"
2. Simple format: Connect to the pins in alphabical sequence "net1,net0,net2" indicating .A(net1),.B(net0),.C(net2)
3. Mixed format: "instance/pin" and net, "U408/Y,U409/Y,net2" indicating A to U408/Y, B to U409/Y and C to net2
4. The "instance/pin" can have sub-instance hierarchy, "u_abc/U408/Y"
@return: Have the new created instance and net name, if the arguments $new_net and $new_instance are empty string.
$return[0] : New created instance.
$return[1] : New created net.
Note: Hierarchical path is supported in any net or instance in the command, for instance, new_net('u_abc/net124', ...
If the command is called in the context of return a scalar, the new created net name will returned back.
The new net is assumed to be driven in the path it is created, for instance, new_net('u_abc/eco12345_net124');
eco12345_net124 should be driven in sub-instance u_abc after it is created.
Examples:
new_net("net123", "NAND2X2", "U_eco_123", ".A(n200),.B(n201)"); # NAND2x2 instance name 'U_eco_123' driving new net 'net123'
new_net("u_abc/net123", "INVX2", "u_abc/U_inv", "n200"); # INVX2 with instance name 'U_inv' is created in u_abc sub-instance
# and the input pin of the invert is driven by n200 in current top level
# port would be created in n200 doesn't have connection to u_abc
new_net("net500"); # Create a new net "net500"
new_net("n200"); # Error, n200 already exists
@return = new_net("", "INVX2", "", ""); # create a new instance with new net tied to output pin, input pin is floating.
# $return[0] is new created instance, $return[1] is new created net.
new_gate
ECO command. Create new gate Usage: @return = new_gate($new_net, $reference, $new_instance, $connections); Note: if the command is called in the context of return a scalar, the new created instance name will returned back. The usage is the same as new_net, except $reference has to be defined, and return back instance if scalar present. Run "help new_net" for detail in shell "GOF >"
new_port
ECO command. Create a new port for the current top level module
Usage: new_port($name, $direction);
$name: Port name
$direction: Direction, input/output/inout
Note: The port name has to be pure words or with bus bit, like, abc[0], abc[1]
Examples:
new_port('prop_control_en', 'input'); # create an input port naming 'prop_control_en'
new_port('prop_state[2]', 'output'); # create an output port with bus bit 'prop_state[2]'
new_port('prop_state[3]', 'output'); # create an output port with bus bit 'prop_state[3]'
del_gate
ECO command. Delete gate Usage: del_gate($inst); $inst: The instance to be deleted.
del_net
ECO command. Delete net Usage: del_net($net); $net: The net to be deleted.
del_port
ECO command. Delete port Usage: del_port($port); $port: The port to be deleted.
buffer
ECO command. Buffer high fanout ECO nets
Usage: buffer($net_names, $buffer_name, $fanout);
$net_names: Net names to be buffered. Use "," to separate multiple nets, like "eco1_net1,reset2"
$buffer_name: The buffer module name from library, leave it blank to automatically extracted.
$fanout: How many fanout to insert a buffer.
Example:
buffer("test_mode", "BUFX6", 10); # for every 10 fanout of test_mode, add a buffer, BUFX6
replace_logic_cone
ECO command. Replace logic cone
Usage: replace_logic_cone($pin_list, @options);
$pin_list: List of the pins whose logic cone will be replaced by logic cone from reference netlist
The format is "sic_cnt_reg_0/D,sic_cnt_reg_1/D,bbr_ccd_reg[0]/D"
'\' should be dropped if the instance has '\' as prefix, E.G. bbr_ccd_reg[0] has real name \bbr_ccd_reg[0] in the netlist
@options:
-help: Print out this information
-keepfreed: Keep freed instances, by defaule all floating gates caused by ECO will be removed
Example:
# Content of replace_logic_cone.pl
undo_eco; # Undo all eco done by previous run
setup_eco("eco_rep_logic_cone"); # 'eco_rep_logic_cone_' will appear as prefix in all new instances and nets
set_inverter("INVX2");
read_library("arm_40_ss.lib"); # It can be loaded in command line by -lib option
my $status = read_design("-golden", "soc_design_resynthesized.gv");
$status = read_design("-revised", "soc_design_released.gv");
set_top("codec_top"); # The module on which the ECO is done
replace_logic_cone("sic_cnt_reg_0/D,sic_cnt_reg_1/D,bbr_ccd_reg[0]/D");
write_verilog("soc_eco.gv");
gexit; # Exit when ECO is done
# End of ECO script
The command line to execute the eco script
gof -run replace_logic_cone.pl
undo_eco
ECO command. Undo eco operations, restore database Usage: undo_eco(); Note: '()' should be added for more stable execution
write_verilog
ECO command. Write out ECOed netlist to a file Usage: write_verilog($verilog_file); $verilog_file: Write out verilog file name, should be different from existing netlist file name.
write_tcl
ECO command. Write out ECO result in Design Compiler tcl script format usage: write_tcl($tcl_script_name); $tcl_script_name: Synopsys Design Compiler tcl script name.
write_cdn
ECO command. Write out ECO result in Cadence SOC Encounter script format usage: write_cdn($soc_encounter_script_name); $soc_encounter_script_name: Cadence SOC Encounter script name.
write_dcsh
ECO command. Write out ECO result in Design Compiler dcsh script format usage: write_dcsh($dc_script_name); $dc_script_name: Synopsys Design Compiler dcsh script name.
sch
Launch schematic to verify ECO
Usage: sch(@instances);
@instances: Instances to be displayed on the schematic
Example
sch("U123", "U456", "inst0");
run
Run GofCall script
Usage: run($script_name);
Example:
run("eco2.pl");
read_design
Read design
Usage: my $status = read_design($file_name, @options);
$file_name: Verilog netlist name
@options:
-golden: The netlist is golden design
-revised: The netlist is revised design
-once: Read the file only once, the file will be bypassed if the command is executed again
Note: If no option is provided, the netlist is assumed 'revised'
$status: If zero, the file is read in successfully
if one, failed to read in the file
Example:
my $status = read_design("-golden", "soc_design_resynthesized.gv");
$status = read_design("-revised", "soc_design_released.gv");
read_library
Read stardard library
Usage: my $status = read_library($file_name);
$file_name: Stardard library file name, having .lib extention
$status: If zero, the file is read in successfully
if one, failed to read in the file
Example:
my $status = read_library("arm_40_hvt.lib");
read_file
Read timing violation report file
Usage: my $status = read_file($file_name, @options);
$file_name: file name
@options:
-format format: accu/pt
accu --- Accucore report file.
pt --- Prime Time report file
$status: If zero, the file is read in successfully
if one, failed to read in the file
Example:
my $status = read_file("soc_primetime_hold.report", "-format", "pt");
Note: Prime Time timing report file should be generated by report_timing command with these options
report_timing -nosplit -path full -delay max/min -input_pins \
-nets -nworst 5 -max_paths 10000 -transition_time -capacitance
read_def
Read DEF file
Usage: my $status = read_def($file_name, @options);
$file_name: file name
@options:
-once: Read the file only once, the file will be bypassed if the command is executed again
$status: If zero, the file is read in successfully
if one, failed to read in the file
Example:
my $status = read_def("soc_top.def"); # Read in soc_top.def
my $status = read_def("soc_top.def", "-once"); # The file is read in only once, the command is bypassed if it is executed again
fix_setup
Fix setup, timing violation report file has to be read first by read_file API before calling this API
Usage: my $status = fix_setup(@options);
@options:
-margin value: Setup violation margin threshold value to insert buffer, default 0
if one path has margin lower than this value, it will be fixed
$status: If zero, fix_setup is successful
if one, fix_setup fails
Example:
my $status = read_file("soc_primetime_setup.report", "-format", "pt");
$status = fix_setup("-margin", 0.2); # The goal is to make all paths have setup slack above 0.2ns
write_verilog("soc_setup_fix.v");
fix_hold
Fix hold, timing violation report file has to be read first by read_file API before calling this API
Usage: my $status = fix_hold(@options);
@options:
-margin value: Hold violation margin threshold value to insert buffer, default 0
if one path has margin lower than this value, buffers are inserted
-buffer name: Name of buffer to be inserted
-bufdelay value: For AccuCore report file. Estimated buffer delay value, in 'ns', 1.0ns by default. E.G. -bufelay 0.9
$status: If zero, fix_hold is successful
if one, fix_hold fails
Example:
# prime time report file
my $status = read_file("soc_primetime_hold.report", "-format", "pt");
$status = fix_hold("-margin", 0.5, "-buffer", "BUFX10"); # The goal is to make all paths have hold slack above 0.5ns
write_verilog("soc_hold_fix.v");
# Or for AccuCore timing report file
my $status = read_file("soc_accurcore_hold.report", "-format", "accu");
$status = fix_hold("-margin", 0.5, "-buffer", "BUFX10", "-bufdelay", 0.9);
write_verilog("soc_hold_fix.v");
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