NanDigits Design Automation

What's New?

Jul 01, 2008. V2.300 released. Download Now!

• Linux 64 bits support
• Break 4G bytes limit in 32 bits.
• Process tens Giga size netlists.

Jun 07, 2008. V2.228 released.

• Hyperlink for information fast accessing.

Apr 03, 2008. V2.227 released.

• Enhanced ECO saving in Verilog.
• Fixed a bug in reading synthesis library.

• Enhanced "Find circuit between points".
• Bug fix in the feature, supporting back slash in instance name.

Nov 14, 2007. V2.225 released.

• Enhanced Perl API interface.   

Oct 16, 2007. V2.224 released.

• Enhanced gate load to take care of multiple trees.
• Combinational logic translating to assignment.
  • GofViewer, Menu Actions->More Tools->Save as

• Enhanced Place and Route algorithm.
• Unlimited undo in schematic creation.
• Multiple gates selection in ECO Add.

Sep 1, 2007. V2.222 released.

• Schematic Auto Place and Route.

Aug 4, 2007. V2.221 released.

• Feature to add/edit/move comments on schematic.
• Complicate gate symbol display on schematic. 
• Out of boundary check in schematic.
  • If user moves gate or comments out of schematic boundary, it will move back automatically.
  • Schematic boundary is defined schematic size that is
  • Horizontal Position is larger than 0, less than max width.
  • Vertical Position larger than 0, less than max height.

July 21, 2007. V2.220 released.

• Extract Logic Cone in Schematic Mode besides Text Mode.
  • Versions before 2.220 support Text Mode only.
• ECO support by both synthesis library and simulation library.
  • Versions before 2.220 support ECO by simulation library only.

July 11, 2007. V2.219 released.

• Fixed a bug in waveform restore file generation . 

May 24, 2007. V2.218 released.

• Floating License Mode Support. 

Mar 31, 2007. V2.217 released.

• Find circuit between two ports/gates. 
• Draw circuit from an input to a flipflop.
• Draw circuit from a flipflop to itself.
• Automatic place all new gates. 

Mar 20, 2007. V2.216 released.

• List Flipflops and Ports as Fanin Fanout Endpoints. 
• Symbol support in synthesis library. 

FEB 15, 2007. V2.215 released.

• Add Optimization option to minimize logic cone size and do incremental changes. See Logic Cone ECO, optimization option.
• In Win32 system, call Win32 printer driver API to do printer setup. 

FEB 04, 2007. V2.214 released.

Jan 16, 2007. V2.213 released.

• Fixed window size abnormal issue in Linux KDE desktop .
• Fixed several corner cases bug in logic cone ECO.
• Logic cone ECO enhancement.

Dec 20, 2006. V2.212 released.

• Matching nets from RTL to Netlist.

• Seamlessly integrated with GOF partial schematic.
• Very convenient to analyze how RTL signals matching to netlist after synthesis.

Nov 18, 2006. V2.211 released.

• Updated Perl APIs.

Nov 12, 2006. V2.210 released.

• Fix a bug in wire generation in ECO.
• Enhanced RTL mode. Line Number Display.

Oct 30, 2006. V2.209 released.

• Add diff untility.
• Diff two text files in GUI mode.
• Specialized in netlist files diff.
• Instance based listing.
• Diff state symbol bar display.
• Diff state highlight color.
• Line number display.

Oct 06, 2006. V2.207/V2.208 released.

• Logic Cone ECO.  Enhancement.

Sep 09, 2006. V2.206 released.

• Logic Cone ECO.
• Read in two netlist files, replace a logic cone in one by the other.
• Check the bundling example, logic_cone_eco.

• Buffers Chain Trace. 
• Auto placement.

Jul 26, 2006. V2.204 released.

• DEF support.
• Net name change  in GofECO.

Jul 22, 2006. V2.203 released.

• Perl Script Interface. Register users only.

Jul 07, 2006. V2.202 released.

• Extract Logic Cone and auto place the gates.

Jun 15, 2006. V2.201 released.

• Equivalent symbol switching according to DeMorgan's Laws.
• Optimize complex gates symbol appearance.
• Several bugs fix in Partial Schematic.

May 20, 2006. V2.200 released.

• Optimize Netlist Processing Engine to occupy less memory when processing large size netlist.
• One experiment shows 378Mbytes netlist uses memory 643Mbytes. The old versions used more than 850Mbytes.

Apr 13, 2006. V2.101 released.

• Fix a bug in multiple netlist files read in.
• Tune up in timing violation controller.

Apr 04, 2006. V2.100 released

• Per a lot of users' request, add line index in RTL viewer.
• RTL viewer color control.
• RTL viewer interface with GTKWave and Verdi.
• Click RTLViewer for detail.

Mar 24, 2006. V2.099 released

• Support Verilog RTL Viewer and net driver trace.
• Fix bug in area calculation. 

Mar 03, 2006. V2.098 released

• Add design statistic to check all leaf cells or specific cells in the design and the hierarchy in the design.
• Fix bug in ECO cell replacement.

• Bottleneck check in Synopsys Primetime Violation Report file.
• Start/Through/End points to define paths.
• Exclude options to mask some paths from report.
• Check new Timing ECO example.

Jan 31, 2006. V2.096 released.

• Physical view cells connectivities and distribution on layout.
• Enhance Clock Tree viewer.
• Add feature in Primetime violation file parsing controller. Check Timing ECO example.

• Improve Timing ECO feature in V2.094.Check Timing ECO example.

Jan 06, 2006. V2.094 released.

• Enhance Timing ECO process in Netlist Time Closure.

Dec 27, 2005.  V2.093 released.

• Add feature of interface to waveform viewer tools GTKWave and Verdi.
• Enhance MacroCell support. To replace a cluster of logic cells (a logic cone) by a MacroCell.
• Enhance Metal layers only ECO.

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