##
## Calculate the clock gated registers percentage 
## You may have to modify $gate_clock_name and $clock_pin to run on your netlist
##
##

use strict;
our $total_reg_num = 0;
my $gated_reg_num = 0;
my $gated_clock_name = "LATCKCX12";
my $clock_pin = "CK";

my @tops = get_roots();
my $top = $tops[0];
my $start = time();
&go_through_module($top);
if($total_reg_num){
  my $ratio = $gated_reg_num / $total_reg_num;
  $ratio *= 100;
  my $st_ratio = sprintf("%2.2f", $ratio);
  print "Overall, gated clock percentage $st_ratio% $gated_reg_num / $total_reg_num\n";
}
my $end = time();
my $delta = $end - $start;
print "Spent $delta seconds to run\n";

##
## recursively go through the modules to get registers
##

sub go_through_module{
  my ($top) = @_;
  set_top($top);
  # get all leaf gates
  my @gates = get_cells;
  my $flops = [];
  my $subtotal = 0;
  my $subgated = 0;
  foreach my $gate (@gates){
    my $ref = get_ref($gate);
    my @type = get_leaf_type($ref);
    # check if the gate is flipflop, the 'ff' is extracted from synthesis library
    # If some sync gates are not defined as flipflop, they should be manually 
    # specified here
    if(grep($_ eq "ff", @type)){
      $total_reg_num++;
      $subtotal++;
            
      my @driver = get_driver("$gate/$clock_pin");
      my $dinst = $driver[0][0];
      if($dinst eq ""){ # not driven by leaf cell
	next;
      }
      my $dmod = get_ref($dinst);
    
      if($dmod eq $gated_clock_name){
	$subgated++;
	$gated_reg_num++;
      }
    }
  }    
  if($subtotal){
    my $ratio = $subgated / $subtotal;
    $ratio *= 100;
    my $st_ratio = sprintf("%2.2f", $ratio);
    print "Module $top has gated clock percentage $st_ratio% $subgated / $subtotal \n";
  }
  ##
  ## Do each hierarchical sub module
  ##
  my @sub_instances = get_instances;
  foreach my $instance (@sub_instances){
    my $sub_module = get_ref($instance);
    &go_through_module($sub_module);
  }
}