In late stage of IC design, netlist is frozen which means no more new synthesis is allowed.  But RTL simulation found a bug which needs rewriting a 8 bits state machine in one module. You have to do netlist ECO. (Engineering Change Orders).  GOF can solve this case easily with different ways based on the bug scenarios.

Scenarios 1: The state machine has following code in RTL

The marked line should be modified to fix bug. After bug fix,  it becomes

Analyze the difference of the lines, only dstini[7] connecting to curindex logic needs to be muxed with 0 and the control bit of mux is (ggpls & shift_enable)

ECO starts:

 

 

 


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