NanDigits Design Automation

One script line to add 3 gates, one port, 4 new wires, 13 connections, 1 disconnection!

A flop's D input should be changed to NAND of three signals, one of the three is the original D input wire.

    The ECO operations are done in line 4

1. undo_eco;
2. set_top("TM_qciflt");
3. setup_eco("eco012345");
4. change_pin("frplx_reg/D","NAND3X4","","-,MXI2X2(qciflsb3b_e,gte_344/gte_con_reg/Q,e_bonn),BUFX6(qcif_s0_good)");

• The first argument is the instance pin, "frplx_reg/D"
• The second argument is the leaf cell "NAND3X4" to drive the D input pin.
• The third argument is the instance for the leaf cell, it's empty "", let the tool pick one instance name.
• The fourth argument is the pin-connections. NAND3X4 has three input pins (A,B,C), so the pin-connections have three parts. Separated by ","
  • Part 1 is "-", which means the original D input wire will be used to connection to A pin of NAND3X4. Read GofCAll APIs for more detail.
  • Part 2 is "MXI2X2(qciflsb3b_e,gte_344/gte_con_reg/Q,e_bonn)". A new gate MXI2X2 is inserted to drive B pin of NAND3X4, the input pins of MXI2X2 is driven by three signals "qciflsb3b_e","gte_344/gte_con_reg/Q" and "e_bon". Out of these three signals, "gte_344/gte_con_reg/Q" is a hierarchical signal which needs a port to pull it to the current hierarchy and the port will be automatically created.
  • Part 3 is "BUFX6(qcif_s0_good)". Wire "qcif_s0_good" is buffered to driver C pin of NAND3X4.

  To run the script, you can use GofCall Graphical mode. In GofViewer, Menu Actions->"GofCall, APIs interactive" to get GofCall window. Press "Advance" button to run in code snip. Or save to a file, key in "run the_script_file" in "GOF > " shell entry to run in batch mode.

  

  Key in "sch eco012345_inst0" in "GOF > " shell entry to launch schematic to verify the ECO on the fly.

  

  After ECO, three new gates, "eco012345_inst0", "eco012345_inst1" and "eco012345_inst2" are created. One port is added to connect "con_bit" from sub-instance "gte_344". Four new wires are created "eco012345_wire0", "eco012345_wire1", "eco012345_wire2" and "con_bit". 13 pin connections are added. And D input of "frplx_reg" is disconnected and reconnected. If converted to Design Compiler TCL script format, there are more than 20 lines!

  current_design gte
  create_port -direction out con_bit
  connect_net [get_nets con_bit] [get_ports con_bit]
  current_design TM_qciflt
  create_net eco012345_wire0
  create_net eco012345_wire1
  create_net con_bit
  create_net eco012345_wire2
  create_cell eco012345_inst0 tmc65nm/NAND3X4
  connect_net [get_nets n3150] [get_pins eco012345_inst0/A]
  connect_net [get_nets eco012345_wire1] [get_pins eco012345_inst0/B]
  connect_net [get_nets eco012345_wire2] [get_pins eco012345_inst0/C]
  connect_net [get_nets eco012345_wire0] [get_pins eco012345_inst0/Y]
  create_cell eco012345_inst1 tmc65nm/MXI2X2
  connect_net [get_nets qciflsb3b_e] [get_pins eco012345_inst1/A]
  connect_net [get_nets con_bit] [get_pins eco012345_inst1/B]
  connect_net [get_nets e_bonn] [get_pins eco012345_inst1/S0]
  connect_net [get_nets eco012345_wire1] [get_pins eco012345_inst1/Y]
  create_cell eco012345_inst2 tmc65nm/BUFX6
  connect_net [get_nets qcif_s0_good] [get_pins eco012345_inst2/A]
  connect_net [get_nets eco012345_wire2] [get_pins eco012345_inst2/Y]
  disconnect_net [get_nets n3150] [get_pins frplx_reg/D]
  connect_net [get_nets eco012345_wire0] [get_pins frplx_reg/D]
  connect_net [get_nets con_bit] [get_pins gte_344/con_bit]
   

  The nested long line can be separated into three small operations, but more manual intervenes are needed to specify the new net names or instance names.

• new_net("eco012345_mx_out", MXI2X2, "", "qciflsb3b_e,gte_344/gte_con_reg/Q,e_bonn");
• new_net("eco012345_buf_qcif_s0_good", "BUFX6", "", "-");
• change_pin("frplx_reg/D","NAND3X4","","-,eco012345_mx_out,eco012345_buf_qcif_s0_good");

Check GofCall Use Cases, or GofCall Overview for more information.