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- Q: What does GOF do?
- GOF, Gates On the Fly, is to trace verilog netlist to draw the gates in partial schematic mode and modify netlist which is also called logic ECO (Engineering Change Order). ECO result can be written out as Synopsys DC-shell tcl format or new netlist.
- Q: Can GOF do hundred gates ECO?
- Yes, GOF can replace a Logic Cone in one netlist by the Logic Cone in another netlist. It's very useful when RTL code has big changes in one state machine generation. Resynthesis has to be done. GOF can figure out the new Logic Cone driving the state machine and replace the old netlist's Logic Cone by new one. GOF is doing ECO Compiler's job in this case. Check Logic Cone ECO for detail.
- Q: Does GOF has script interface?
- GOF provides several useful Perl APIs. Check GOF Perl Interface for detail.
- Q: What OS platforms does GOF support?
- Currently GOF supports Linux and Windows platform.
- Q: When run gof -v lib.v netlist.v, nothing appears in GofViewer window.
- netlist.v not exists.
- Q: I have a bunch of files with extention of .v and .vlib in a library directory, how to load them as library files?
- gof +libext+.v+.vlib -y the_library_directory -v the_other_library_file.vlib netlist.v Or check Usage for detail.
- Q: How to bring up schematic?
- Several ways to bring up schematic. Double click leaf cell name or instance to pop out GofTrace Schematic Window, or click menu Tools->'Goftrace Schematics'. See launch GofTrace for detail
- Q: How large netlist GOF can handle?
- Unlimited size, as long as the machine has enough memory and CPU can access. 500M bytes netlist will use 1.0G to 1.8G memory space.
- Q: What's the GOF's advantage comparing with nECO from Novas software?
- More ECO operations.
- Replace cluster of logic which nECO can't.
- Cell insertion and replacement.
- nECO has only cell adding, line disconnecting and connecting.
- More powerful partial schematic. nECO can't move cell's position, while GOF can readjust cells position and connections after schematic is drawn so that all items involving in ECO are close to each other.
- Q: What is Timing ECO? How is GOF used in Timing ECO?
- In netlist timing closure period, ASIC designers have to do a lot of timing ECOs according to timing violations report file.
- Timing ECO process is to fix setup or hold timing violations without changing RTL functions.
- It can be inserting buffers inverts or increasing/decreasing cells drive strength or duplicating the heavy fanout cells to off-load fanouts.
- But the timing violations report file normally gives hundreds thousands of violated paths and manually fixing even one path takes long time.
- Making things more complicated is a lot of paths have a lot shared cells in sub-paths.
- Handle timing ECO efficiently.
- Parse synopsys PrimeTIme timing violation report file.
- Summary path violations and bottlenecks.
- And feed violated paths into GOF ECO flow automatically.
- Users have very clear view of the violated path connectivity and relation with other paths in a schematic.
- Check one example of Timing ECO.
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